Brief Overview - Click on the week for detailed information
Week 1 -	1. Work on research proposal. 2. Research on possible topics including FPGA, UART, infrared and some mechanical parts
Week 2 -	1. Finalized on project topic. 2. Start initial design.
Week 3 -	1. Block Diagram 2. Project Proposal 3. Initial VHDL design with ports specs.
Week 4 -	1. Meet with TA. 2. Implement proposed protocol in VHDL
Week 5 -	1. Plan and Implement Acquire Unit
Week 6 -	1. Compiled and Simulated Acquire Unit
Week 7 -	1. Refined Acquire Unit's timing and parameterized acquisition frequency.
Week 8 -	1. Finished Acquire Unit Simulation 2. Finished Packaging Unit Simulation
Week 9 -	1. Modified Acquire Unit for Reset signal and 4-bit per channel protocol. 2. Modified Packaging Unit for Reset signal 3. Modifying Main Unit for simulation of complete VHDL model
Week 10 -	1. Created Decoder Module 2. Completed Logic Analyzer 3. Write Final Report