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Senior
Design Project -
Project Description
| Partners: |
Ilya
Katsnelson
Toan Nguyen
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PowerPoint
Proposal Presentation |
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| Description:
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Logic Analyzer
using FPGA
User will be using Palm to initialize, configure, and specify
triggering event on the Palm. The Palm will send that
information to FPGA through UART. FPGA will change its
state from 'idle' to 'armed' state to look for the triggering
condition. When the triggering condition is met, it
changes from 'armed' state to 'acquire' state to acquire
data. The data will be put into FIFO buffer to be sent
back to the Palm. When the buffer becomes full, data is
sent via UART back to the Palm. |
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Figure 1. Project Block Diagram
Figure 2. Project Module Diagram
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We are planning on
using a function generation to generate the input. We
are trying to integrate UART into FPGA to reduce delay and
stablize the circuit. |
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Figure 3. Main State Diagram
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This is the main
state. VHDL model will follow this state diagram.
1. When the device first start, it starts at 'INITIAL'
state. Registers will be initialized.
2. After initialization, device enters 'IDLE' state to wait
for any command from the user.
3. When user specifies a triggering condition, device enters
'ARM' state.
4. When triggering condition is met, device enters
'ACQUISITION' state and acquires data from the input
device. Data is put in FIFO buffer, and when the buffer
becomes full, data is sent to the Palm. |
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