Integrated Management of Power Aware Computing and Communication Technologies

Dexin Li, Pai H. Chou, Nader Bagherzadeh, and Fadi Kurdahi, "Power-Aware Architecture Synthesis and Optimization for Mission-Critical Embedded System", submitted to DAC 2001


This paper presents a design tool that bridges the policy-mechanism gap by automating the mapping from high-level power/performance constraints to the low-level mechanisms. Given a workload and power constraints, this tool will compute an optimal bus topology that will enable bus segmentation, voltage scaling, and many novel power-management techniques to be applied together, as driven by the application constraints. It also synthesizes a low-level power manager that implements high-level power/performance constraints in terms of architectural primitives. These include changing power modes of the components and configuring the bus topology. We demonstrate the effectiveness of this technique by mapping the Mars Pathfinder application onto the NASA X-2000 architecture.


Bus architecture modeling

Algorithm and methodology

Experiment results

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