Index -- All Volumes

Symbols

!GND node 3-17
$ comment delimiter 3-9
$installdir installation directory 3-50
* comment delimiter 3-9

A

A model parameter 14-19
A2D
   function 5-50 , 26-4
   model parameter 5-50
   output model parameters 5-54
    See also mixed mode
.a2d file 3-55 , 3-57 , 5-50
AB model parameter 15-35
ABS element parameter 26-12 , 26-18 , 26-23 , 26-28
abs(x) function 7-9
ABSH option 9-20 , 9-38 , 10-36 , 11-15 , 12-7
ABSI option 9-20 , 10-35 , 10-37
   KCLTEST setting 9-21 , 10-26
ABSMOS option 9-20 , 10-35 , 10-37
   KCLTEST setting 9-21 , 10-26
absolute
   power function 7-9
   value function 7-9
   value parameter 26-12 , 26-18 , 26-23 , 26-28
ABSTOL option 9-21 , 10-22
ABSV option 9-38 , 10-35 , 11-15
ABSVAR option 9-43 , 9-46 , 11-15 , 11-18 , 11-27
ABSVDC option 9-21 , 10-38
AC
   analysis 8-3
      circuit and pole/zero models 29-47
      distortion 12-9
      MOSFETs 20-24
      noise 12-11
      RC network 2-2
   control options 12-7
   magnitude calculation 9-5 , 9-39 , 12-7
   network analysis 12-14
   optimization 12-4
   output
      calculation method 9-5 , 9-39 , 12-7
      variables analysis 8-29
   phase calculation 9-5 , 9-39 , 12-7
   resistance 12-3
      parameter 26-74
      transmission lines C-19
   small signal analysis 9-38
      flow 12-2
   sources 5-5
.AC statement 13-5 , 13-39
   external data 3-22
   keywords 12-5
   parameters 12-5
   uses 12-4
.ac# file 3-55 , 3-57
accessing customer support vi
ACCT option 8-16 , 9-5
ACCURACY
   element parameter 29-10
accuracy
   control options 10-36
   simulation time 10-35
   tolerance 10-34
ACCURATE option 9-38 , 11-16 , 11-27
ACM 17-3
   model parameter 11-27 , 17-3 , 20-27
   MOS diode 20-31 , 20-34 , 20-37 , 20-41
   parameter 20-9 , 20-26
      equations 17-22
acos(x) function 7-9
ACOUT option 8-30 - 8-32 , 9-5 , 9-39 , 12-7
adder
   circuit 31-3
   demo 31-3
   NAND gate binary 31-4
   subcircuit 31-3
admittance
   AC input 8-34
   AC output 8-34
   Y parameters 8-29
AF model parameter 12-13
AGAUSS keyword 13-16
ALFA, .FFT parameter 28-8
algebraic
   equations, example 24-11
   expressions 7-8
   models 11-27
algorithms
   Damped Pseudo Transient algorithm 10-48
   DVDT 9-43 , 9-48 , 11-13 , 11-15 , 11-33 , 11-34
   GEAR 9-48 , 11-13 , 11-29
   integration 11-29
   iteration count 11-33
   Levenberg-Marquardt 13-53
   local
      truncation error 9-41 , 9-48 , 11-13 , 11-19 , 11-33 , 11-34
         timestep 9-40 , 11-18
   Muller 27-3
   pivoting 9-24 , 9-26 , 10-27
   timestep control 9-44 , 11-12 , 11-32 , 11-33 , 11-35
   transient analysis timestep 9-48 , 11-13
   TRAP 9-48 , 11-13
   trapezoidal integration 9-49 , 11-14 , 11-29
ALL keyword 10-6 , 10-13
ALPHA model parameter 14-19
.ALTER
   blocks 3-41 - 3-42
   statement 3-40
      failure 8-18
      limit 8-18
      multiple .ALTER's 3-42
      PCI modeling 25-44
      with .DEL LIB 3-42
alternate saturation
   model parameters
      LEVELs 6, 7 21-57
AM
   behavioral 26-62
   modulation frequency 28-13
   source function 5-22 , 5-22
AMD models 20-5 , 20-6
AMI gate capacitance model 20-94
AMP model parameter 26-66
amplifiers, pole/zero analysis 27-12 , 27-14
analog
   behavioral
      elements 26-53
      modeling 26-4
   circuit simulation of a digital system 25-4
   device models D-5
Analog Artist interface 9-11
   output data format 9-12
    See also Artist
Analysis
   FAQ A-2
analysis
   AC 8-3
   accuracy 10-34 - 10-35
   circuit model 29-47
   data driven 13-2 , 13-3 , 24-9
   DC 8-3
   distortion 12-9
   element template 8-4
   FFT 11-44
      example
         AM modulation 28-13
         modulator/demodulator 28-16
         test circuit 28-24
      windows 28-3
   Fourier 11-37
   initialization 10-3
   inverter 2-7
   .MEASURE statement 8-4
   Monte Carlo 13-3 , 13-14 , 13-14 - 13-34 , 18-52
   MOSFETs
      AC 20-24
         noise 20-25
      transient 20-23
   network 12-14
   noise 16-58
   optimization 13-39
   parametric 8-4
   pole/zero 10-21 , 27-1
      example
         active low-pass filter 27-15
         CMOS differential amplifier 27-12
         high-pass Butterworth filter 27-10
         Kerwin's circuit 27-8
         low-pass filter 27-5
         simple amplifier 27-14
      model 29-47
      overview 27-2
      using Muller method 27-3
   pulse width 30-16
   RC network
      AC 2-2
      transient 2-5
   setup time 30-10
   spectrum 28-1
   statistical 13-8 - 13-34
   Taguchi 13-2
   temperature 13-2 , 13-5
   timing 30-1
   transfer function (.TF) 26-46
   transient 8-3 , 11-3
   worst case 13-2 , 13-8 - 13-34
   yield 13-2
arccos(x) function 7-9
arcsin(x) function 7-9
arctan(x) function 7-9
area
   calculation method See ACM
   JFETs and MESFETs
      equations 17-22 - 17-24
      units 17-22 , 17-24
AREA capacitor parameter 15-6
arithmetic operators 7-9
ARTIST option 9-11 , 9-12
ASCII output data 9-11 , 9-12
ASIC
   device libraries 3-51
   vendor libraries 3-51
asin(x) function 7-9
ASPEC
   AMI model 20-5
   compatibility 9-13 , 20-3 , 20-37 , 21-86
   option 9-13 , 20-11
asterisk comment delimiter 3-9
asymptotic waveform evaluation 29-2
   transfer function 29-35
AT keyword 8-42
AT1 model parameter C-36
atan(x) function 7-9
ATEM characterization system 3-50
ATLEN model parameter C-36
AUNIF keyword 13-16
AURORA user's group vi
autoconvergence 10-42
   algorithm 9-31 , 10-39
   disabling 9-31 , 10-39
automatic model selection
   failure D-3
   multisweep or .TEMP effect D-4
    See also model selection
AUTOSTOP option 9-41 , 11-20 , 11-25 , 24-9 , 26-74
AV model parameter 26-67
AV1K model parameter 26-67
AvanLink
   Cadence products B-2
   DA
      design flow B-10
      environment B-9
      Netlister B-12
      schematic B-10
      simulation B-12
   design flow B-4
   environment B-3
   library operations B-5
   Mentor Graphics products B-8
   netlist B-6
   schematic B-5
   simulation B-7
Avant! web site vi
AvanWaves waveform display B-7 , B-12
AVD model parameter 26-67
average deviation 13-3
average value, measuring 8-46
AVG keyword 8-47
AWE See asymptotic waveform evaluation

B

B# node name in CSOS 3-19
backslash continuation character 3-3 , 7-8
   double 7-8
   in input files 3-3
BADCHR option 3-3 , 9-15
bandwidth C-79
BART FFT analysis keyword 28-8
Bartlett FFT analysis window 28-4 , 28-5 , 28-26
base
   charge equations 16-32
   collector capacitance 16-36
   resistance equations 16-32
base-collector junction 16-5
base-emitter
   capacitance equations 16-34
   junction 16-5
basic model parameters
   BJTs 16-6
   JFETs TOM model 17-46
   MOSFETs
      LEVEL 1 21-2
      LEVEL 13 21-107
      LEVEL 2 21-7 - 21-8
      LEVEL 27 21-138
      LEVEL 28 21-152
      LEVEL 3 21-19
      LEVEL 38 21-164
      LEVEL 39 21-179
      LEVEL 40 21-207
      LEVEL 47 22-2
      LEVEL 49, 53 22-34
      LEVEL 5 21-34
      LEVEL 50 22-56
      LEVEL 57 22-117
      LEVEL 58 22-134
      LEVEL 8 21-89
      LEVELs 6, 7 21-52 - 21-54
behavioral
   741 op-amp 26-76
   amplitude modulator 26-62
   AND and NAND gates 26-31
   BJTs
      modeling 26-92
      phase detector model 26-97
   CMOS inverter 26-46
   comparator 26-79
   components 26-40
   current source 5-34 , 26-16
   data sampler 26-63
   device models D-8
   differentiator 26-55
   D-Latch 26-32
   double-edge triggered flip-flop 26-36
   elements
      analog 26-53
      using 26-3
   flip-flop 26-36
   gates 26-31
   integrator 26-53
   LC oscillator 26-83
   look-up tables 26-40
   n-channel MOSFETs 26-34 , 26-42
   p-channel MOSFETs 26-34
   phase detector model 26-88
   phased locked loop 26-88
   ring oscillator 26-50
   silicon controlled rectifier 26-59
   transformer 26-57
   triode vacuum tube 26-60
   tunnel diode 26-58
   VCO model 26-81
   voltage source 5-29 , 26-11
   VVCAP model 26-84
Berkeley
   BSIM3-SOI model 22-114
   junction model 22-24
   NonQuasi-Static (NQS) model 22-23
beta degradation 16-6
BETA keyword 12-14
Biaschk 11-9
BiCMOS
   circuits 16-2
   devices 16-2
bidirectional circuits, wire RC model 14-2
binary
   output data 9-12
   search 30-6 - 30-12
Bipolar Junction Transistors. See BJTs
bisection
   data, printing 9-8
   error tolerance 30-8
   function 30-1
      syntax 30-7
   methodology 30-5
   overview 30-2
   pass-fail method 30-5
   requirements 30-6
   violation analysis 30-4
BISECTION model parameter 30-7
BJTs
   base
      charge equations 16-32
      push-out effects 16-50
      width modulation model parameters 16-9
   base-collector
      depletion capacitance equations 16-37
      diffusion capacitance equations 16-36
   base-emitter
      depletion capacitance equations 16-35
      diffusion capacitance equations 16-34
   beta
      degradation 16-6
      temperature equations 16-42 - 16-46
   capacitance temperature equations 16-46
   conductance 16-21 , 16-22
   current
      equations 16-29
      flow 8-24
   DC 16-6
      models
         equations 16-29
         parameters 16-6
   element template listings 8-59
   elements, names 4-15
   energy gap temperature equations 16-42
   equations 16-28
   equivalent circuits 16-20 , 16-21
   excess phase equation 16-39
   EXPLI 9-19
   geometric 16-6
   high current Beta degradation parameters 16-10
   junction capacitance
      equations 16-37
      model parameters 16-11
   junction capacitor 16-6
   LEVEL 2
      model parameters 16-13
      temperature equations 16-49
   LEVEL 4, model parameters 16-63 - 16-66
   LEVEL 8 HiCUM
      parameters 16-95
   LEVEL 8, HiCUM 16-93
   low current Beta degradation parameters 16-9
   .MODEL statement 16-3
   models
      constants (table) 16-27
      convergence 16-3
      names 16-4
      parameters 16-6 , 16-63 - 16-66
      quasi-saturation 16-50
      statement 16-4
      transistor D-9
      variables (table) 16-25
   noise 16-6
      equations 16-40
      model parameters 16-13
      summary printout 16-41
   npn identifier 16-4
   parasitic capacitance 16-6
   parasitics
      capacitance model parameters 16-12
      resistance model parameters 16-10
      resistor temperature equations 16-49
   pnp identifier 16-4
   power dissipation 8-26
   quasi-saturation model 16-50
   resistor 16-6
   saturation temperature equations 16-42 - 16-46
   scaling 16-20
   S-parameters, optimization 13-60
   subcircuits, scaled 16-55
   substrate
      capacitance equations 16-39
      current equation 16-31
   temperature
      capacitance equations 16-46
      compensation equations 16-42
      effect parameters 16-14
      parasitic resistor 16-49
      saturation equations 16-44
   transit time 16-6
      model parameters 16-12
   variable base resistance equations 16-32
BKPSIZ option 9-41 , 11-20
BLACK FFT analysis keyword 28-8
Blackman FFT analysis window 28-4 , 28-27
Blackman-Harris FFT analysis window 28-4 , 28-28
bond wire example 31-12
branch current
   error 9-20 , 9-21 , 10-22 , 10-37
   output 8-22
branch matrix C-33
breakpoint table
   reducing size 11-36
   size 9-41 , 11-20
BRIEF
   keyword 10-6
   option 9-2 , 9-6 , 9-7 , 9-8 , 9-9
Broyden update data, printing 9-8
BSIM model 21-101
   equations 21-112
   LEVEL 13 3-31 , 20-5
      example 21-121
   VERSION parameter effects 21-111
BSIM2 LEVEL 39 model 3-31
BSIM2 model 21-179
   equations 21-186
   LEVEL 39 20-6
   VERSION parameter effects 21-193
BSIM3 model
   equations 22-10
      Leff/Weff 22-9
   LEVEL 47 20-6
   SOI FD 22-147
BSIM3 SOI FD
   parameters 22-149
   template output 22-157
BSIM3 Version 2 MOS model 22-2
BSIM3v3 model
   MOS 22-19
   with Star-Hspice 22-32
BSIM4 model 22-66
   parameters 22-67
buffer 4-27 , 19-6
   differential pins 19-36
   ECL
      input 19-19
      input/output 19-23
      output 19-20
      tristate 19-21
   IBIS 19-1
   input 19-6 , 19-7
      example 19-42
   input/output 19-16
      open drain 19-18
      open sink 19-18
      open source 19-19
      syntax 19-15
   open
      drain 19-18
      sink 19-18
      source 19-18
   output 19-8 , 19-9
      example 19-42
   scaling strength 19-38
   tristate 19-11 , 19-12
bulk
   charge effect 20-3
   semiconductor devices 17-2
   transconductance, MOSFETs 20-23
BULK wire model parameters 14-4
Burr-Brown devices D-9
bus notation 5-68
BUS wire RC model 14-2
Butterworth filter pole/zero analysis 27-10
BV diode model parameter 15-4
BW model parameter 26-69
BYPASS option 9-42 , 11-11 , 20-11 , 20-13
BYTOL option 9-42 , 11-16

C

C2 model parameter 26-68
Cadence
   Analog Artist
       See Artist, Analog Artist
      with AvanLink B-2
   Composer, with AvanLink B-2
   Opus 9-11
   WSF format 9-11
capacitance
   base collector 16-36
   CAPOP model selector 20-7
   charge tolerance, setting 9-39 , 11-16
   circuit C-33
   control options 20-68
   CSHUNT node-to-ground 9-39 , 11-12
   DCAP 15-5 , 16-2
   DCCAP 15-5 , 16-2
   diode, Fowler-Nordheim 15-49
   distribution for wire RC model 14-2
   effective 14-10
   element parameter 4-5
   equations
      BJTs 16-34 , 16-35 , 16-36 , 16-37
      depletion 15-26
      diffusion 15-26
      diode 15-25
      metal and poly 15-27
      MOSFETs 20-46
   GMIN 16-2
   GMINDC 16-2
   input-output ratio 14-2
   JFETs 17-6
   JFETs and MESFETs 17-6 , 17-25 - 17-30
      CAPOP=2 parameters 17-29
      equations 17-6
      gate to drain 17-5
      source to gate 17-5
   junction, internal collector 16-37
   manufacturing variations 13-24
   matrixes C-52
   model 14-9
      parameters 14-9 , 20-27 - 20-28 , 20-69
      selection 20-57
   MOSFETs
      AC gate 20-97
      BSIM model 21-117
      diodes 20-46
         equations 20-106
      equations 20-74 - 20-98
      gate capacitance 20-66
         example 20-64
         length/width 20-97
         models 20-57
         SPICE Meyer 20-74
      Meyer model 20-57 , 20-71
      models 20-57
   multiconductor C-32
   overlap 20-73
   parameters 14-9
      BJTs 16-11
      junction 15-12
      Meyer 20-71
      MOSFETs
         Cypress 21-169
         IDS LEVEL 5 21-36
         LEVEL 38 21-169
         LEVEL 49 and 53 22-39
         LEVEL 5 21-36
         LEVEL 57 22-124
   parasitic 14-2 , 16-12
   pins 24-6
   plotting 20-66
   scale factor, setting 9-35 , 10-31
   substrate 16-38
   table of values 9-28 , 10-22
   temperature 14-11
      equations 14-11
         BJTs 16-46
   voltage variable 26-84
   wire, equations 14-6
capacitance-voltage plots, generating 9-28 , 10-23
capacitor
   BJT 16-6
   conductance requirement 10-47
   current flow 8-23
   DC sweep evaluation 16-34
   device
      equations 14-10
      model 14-9
   element 4-4 , 14-9
      template listings 8-55
   equation selector option 15-5
   equations 17-6
   models 3-30
      gate 20-57
      list 20-7
      name 4-5
      SPICE 17-5
   parameters
      junction 16-11
      metal and poly 15-13
   switched 29-48
   temperature, equations 14-8
   transcapacitance 20-59
   voltage controlled 5-35 , 5-40
CAPL model parameter C-36
CAPOP model parameter 11-27 , 17-3 , 20-7 , 20-57 , 20-69
   XPART 20-72
   XQC 20-72
CAPTAB option 9-28 , 10-22
cascoding, example 20-55
CASMOS
   GEC model 20-5
   GTE model 20-5
   Rutherford model 20-6
CBD model parameter 20-27
CBS model parameter 20-27
CCCS
   element parameter 26-28
   syntax 5-46
CCVS 5-42
   element parameter 26-23
   syntax 5-42
CDB model parameter 20-28
cell characterization 13-2 , 24-9
CENDIF optimization parameter 13-41
CEXT model parameter C-15 , C-24 , C-26 , C-28
channel length modulation, MOSFETs
   equations
      LEVEL 2 21-15
      LEVEL 3 21-26
      LEVEL 38 21-175
      LEVEL 5 21-48
      LEVEL 6 21-80
      LEVEL 8 21-98
   parameters
      LEVEL 6 21-80
      LEVEL 8 21-93
characteristic impedance C-73
characterization of models 10-14
charge conservation 20-91
   capacitance 20-87
charge tolerance, setting 9-39 , 11-16
CHGTOL option 9-39 , 11-16 , 11-34
circles, defining 18-39
circuits
   adder 31-3
   BiCMOS 16-2
   BJT 16-20 , 16-21
   design
      nonplanar and planar technologies 20-15
      wave processes 20-15
   ECL 16-2
   inverter, MOS 2-7
   model 29-43
      AC analysis 29-47
      transient responses 29-46
   nonconvergent 10-51
   RC
      line 29-33
      network 2-2
   reusable 3-47
   simulating
      with Signetics drivers 25-18
      with Xilinx FPGAs 25-22
   subcircuit numbers 3-18
   temperature 13-5 , 13-6
   test, FFT analysis 28-24
   TTL 16-2
    See also subcircuits
CJ model parameter 20-28
CJA model parameter 20-28
CJBR model parameter 15-36
CJGATE model parameter 20-28
CJGR model parameter 15-36
CJP model parameter 20-28
CJSR model parameter 15-36
CJSW model parameter 20-28
CLEN model parameter C-36
CLOAD model parameter 5-54
clock
   frequency C-79
   skew 25-6
CLOSE optimization parameter 13-41
CMI
   function calling protocol 23-36
   models, simulations 23-4
   supported platforms 23-5
   testing 23-12
   variables 23-18
CMI_AssignInstanceParm 23-23
CMI_AssignModelParm 23-22
CMI_Conclude 23-35
CMI_DiodeEval 23-27
CMI_Evaluate 23-26
CMI_FreeInstance 23-32
CMI_FreeModel 23-32
CMI_Noise 23-29
CMI_PrintModel 23-31
CMI_ResetInstance 23-22
CMI_ResetModel 23-20
CMI_SetupInstance 23-25
CMI_SetupModel 23-24
CMI_Start 23-35
CMI_WriteError 23-33
CMOS
   differential amplifier, pole/zero analysis 27-12
   output driver demo 31-12
   tristate buffer, optimization 13-55
CMRR
   model parameter 26-68
   specification 26-5
CMULT model parameter C-15 , C-24 , C-26 , C-28
CO option 8-14 , 9-6
coax
   models C-57
    See also transmission lines
coefficients
   Laplace 29-23
   transfer function 29-21
collector-substrate junction 16-5
column laminated data 3-28
comlinear device models D-10
commands
   Hspice 3-58 - 3-62
      arguments 3-59
      examples 3-62
      options 3-60
   limit descriptors 8-18
   output 8-2
comment line (digital vector files) 5-62
comments 3-9
common
   emitter gain 31-20
   model interface (CMI) 23-1
Common Simulation Data Format 9-11
COMP model parameter 26-66 , 26-68
comparators
   behavioral models 26-65
   model 26-79
complex poles and zeros 29-30
compression of input files 3-2
computer platforms for HSpice 1-6
concatenated data files 3-26
conductance
   BJTs 16-21 , 16-22
   current source, initialization 9-33 , 10-40
   diodes 15-17
   for capacitors 10-47
   GMIN 15-5
   GMINDC 15-5
   JFETs 17-6
   JFETs and MESFETs 17-6 , 17-9
   matrices 18-4
   minimum, setting 9-39 , 11-21
   models 9-31 , 10-24
   MOSFETs 20-22 , 20-54
      nodes 9-33 , 10-40
   multiconductor C-32
   negative, logging 9-15
   node-to-ground 9-34 , 9-39 , 10-25 , 11-12
   output, negative, preventing 21-121 , 21-193
   pn junction 10-54
   scale, setting 9-35 , 10-31
   sweeping 9-33 , 10-24
configuration file 3-54
continuation character, parameter strings 7-8
continuation of line (digital vector file) 5-62
control characters in input 3-3
control options 17-6
   accuracy 9-20 , 10-36
      AC 9-38 , 9-38 - 9-41
      defaults 11-35
   algorithm 9-47 - 9-49
   algorithm selection 10-22
   analysis 9-13 - 9-15
   ASPEC 20-11
   BYPASS 20-11
   capacitance 20-68
   convergence 9-29 - 9-35 , 10-36 , 15-5
      DC 10-22
   DC convergence 10-22
   DC operating point analysis 10-22
   defaults 9-2
   error 9-15
   FAQ A-27
   initialization 10-22
   input and output 9-5 - 9-10 , 9-28 , 9-50
   interface options 9-11 - 9-13
   keyword table 9-3
   limit 11-20
   matrix-related 9-23 - 9-27
   method 11-11
   pole/zero 9-35 - 9-37 , 27-4
      analysis 10-31 - 10-33
   printing 8-14
      values of 9-9
   setting 9-2 , 15-4
   speed 9-41 - 9-43
   table 9-5
   timestep 9-43 - 9-47
   tolerance 11-15
   transient analysis
      limit 11-20 - 11-23
      method 11-11 - 11-14
      tolerance 11-15 - 11-20
   version 9-15
controlled sources 5-24 , 26-4 , 26-6
   element statement 5-24 , 26-7
conventions
   bias polarity 23-42
   source-drain reversal conventions 23-43
CONVERGE option 9-29 , 9-32 , 10-38 , 10-42 , 10-48
convergence
   BJT model 16-3
   control options 10-36
   current 9-20 - 9-22 , 9-38 , 9-39 , 9-40 , 10-36 , 10-39 , 10-40 , 11-15 - 11-18 , 12-7 , 12-8
   ensuring 10-23
   for optimization 13-43
   increasing iterations 10-23
   JFETs and MESFETs 17-6
   MOSFETs diodes 20-26
   problems 10-49
      analyzing 10-49
      autoconverge process 10-42
      causes 10-51
         by BYPASS 9-42 , 11-11
      changing integration algorithm 9-49 , 11-14
      CONVERGE option 10-48
         solutions 9-29 , 9-32 , 10-38
      DCON setting 9-30 , 10-39 , 10-44
      decreasing the timestep 9-44 , 11-21
      diagnosing 10-49 - 10-54
      diagnostic tables 10-49
      diodes 15-5
      floating point overflow 10-48
      GMINDC ramping 10-44
      internal timestep too small 9-48 , 11-13
      .NODESET statement 10-10
      nonconvergent node listing 9-31 , 10-39
      op-amp models 26-66
      operating point Debug mode 10-7
      pole/zero analysis 27-3
      reducing 10-45
      setting DCON 9-31 , 10-39
   steady state 9-33 , 10-24
core
   Jiles-Atherton 14-12
      ferromagnetic 14-19
      model parameters 14-16
   magnetic 14-12
      element output 14-16
      model parameters 14-14
   model parameters 14-16
      A 14-19
      ALPHA 14-19
      MS 14-19
CORKD model parameter C-15 , C-25
cos(x) function 7-9
cosh(x) function 7-9
coupled line noise simulation example 25-27
CPTIME option 9-11
CPU time
   limiting 9-11
   reducing 9-8
   setting maximum 9-11
critical frequency 29-5
CROSS keyword 8-41
crosstalk C-78
CSB model parameter 20-28
CSCAL option 9-35 , 10-31 , 27-4
CSDF option 9-11
CSHDC option 9-29 , 10-23
CSHUNT option 9-39 , 11-12
CUR element parameter 26-18
current
   ABSMOS floor value for convergence 9-22 , 10-41
   branch 8-23
      current error 9-20 , 10-22 , 10-37
   controlled
      current sources 5-46 , 26-6 , 26-7 , 26-27
         element template listings 8-57
      elements 26-6
      sources 5-24
      voltage sources 5-42 , 26-6 , 26-23
         element template listings 8-57
   convention
      BJTs 16-20
      JFETs 17-7
      MOSFETs 20-21
   diodes 15-16
   epitaxial 16-51
   in HSPICE elements 8-23 -??
   operating point table 10-6
   output 8-21
      element branches 8-22
   sources 5-34
CURRENT keyword 10-6
Curtice model 17-3 , 17-21 , 17-22
customer support vi
CUT optimization parameter 13-42
C-V plots 31-7
   generating 9-28 , 10-23
CVTOL option 9-18
Cypress model 20-5 , 21-162

D

D12 model parameter C-28
D2A
   function 5-50 , 26-4
   input model parameters 5-51
   model parameter 5-50
    See also mixed mode
.d2a file 5-50
Dallas Semiconductor model 20-5
Damped Pseudo Transient algorithm 10-48
data
   driven
      analysis 13-2 , 13-3 , 24-9
      PWL source function
         PV parameter 5-19
         TIME parameter 5-19
   encryption E-1
   files, disabling printout 9-6 , 9-8
   flow, overview 1-9
   sampler, behavioral 26-63
   sheet parameters 24-1 , 24-2
DATA keyword 3-21 , 10-15 , 11-5 , 12-5
.DATA statement 3-21 , 24-9
   data-driven analysis 3-21
   datanames 3-22
   external file 3-25 , 3-27
   for sweep data 3-22
   inline data 3-23
   inner sweep example 3-24
   outer sweep 3-25
   outer sweep example 3-25
   sweep 3-25
datanames 3-22
db(x) function 7-10
DC
   analysis 8-3 , 10-19 - 10-21
      capacitor conductances 10-47
      decade variation 10-16
      initialization 9-30 , 10-22 , 10-23
      iteration limit 9-23 , 10-25
      linear variation 10-16
      list of points 10-16
      octave variation 10-16
      sensitivity 10-19
      transfer function 10-20
   BJT 16-6
   convergence control options 10-22
   current 20-45
   equations
      BJTs 16-29
      JFETs and MESFETs 17-31 - 17-34
   errors, reducing 10-45
   operating point
      analysis 10-6
      bypassing 11-3
      initial conditions file 3-54
       See also operating point
   optimization 10-15
   parameters
      JFETs
         LEVEL 1 17-19
         LEVEL 2 17-19 - 17-20
         LEVEL 3 17-21 - 17-22
      MOSFETs 20-27
         LEVEL 57 22-118
   sensitivity analysis 10-19
   small-signal analysis 10-20
   sources 5-5
   sweep 10-14
   transfer function 10-20
.DC statement 10-14 , 13-5 , 13-39
   external data with .DATA 3-22
DCAP 15-5 , 16-2
   equation selector 16-3
   option 15-5
      JFETs and MESFETs
         capacitance 17-6
         models 17-6
      overriding in BJTs models 16-3
DCCAP 15-5 , 16-2
   option 9-28 , 10-23 , 15-5 , 16-34 , 31-7
      JFETs and MESFETs capacitance 17-6
DCFOR option 9-29 , 10-23
DCHOLD option 9-30 , 10-23
DCON option 9-30 , 10-39 , 10-42
DCSTEP option 9-31 , 10-24 , 10-47
DCTRAN option 9-32 , 10-39
.DCVOLT statement 10-9
DDL 3-50 , 26-5
   DDLPATH variable 3-51
   models 31-20
DDLPATH environment variable 3-51 , 31-20
DEBUG keyword 10-7
DEC keyword 10-16 , 11-6 , 12-6
decibel function 7-10
decoupling methods 25-6
DEF model parameter 26-68
DEFAD option 9-18 , 20-11
DEFAS option 9-18 , 20-11
DEFAULT_INCLUDE variable 3-54
DEFL option 9-18 , 20-11
DEFNRD option 9-18 , 20-11
DEFNRS option 9-18 , 20-11
DEFPD option 9-18 , 20-11
DEFPS option 9-18
DEFW option 7-16 , 9-18 , 20-11
.DEL LIB statement 3-6
   in .ALTER blocks 3-41
   with .ALTER 3-42
   with .LIB 3-42
   with multiple .ALTER statements 3-42
DELAY
   element parameter 26-12 , 26-18 , 26-24 , 26-28
   model parameter C-36
delays
   causes 25-3
   derating curve 24-4
   element example 5-40
   Elmore 29-33
   group 8-33 , 9-51 , 12-8
   measuring 8-39
   plotting 24-5
   problems and solutions 25-3
   simulation example 24-2 , 24-9
   time (TD) 8-33
   transmission lines C-37
   types 25-6
DELEN model parameter C-36
DELF element parameter 29-6 , 29-10
DELMAX option 9-43 , 9-46 , 11-20 , 11-23 , 11-26 , 11-35 , 11-38
   ideal delay elements 11-26
   oscillator circuits 11-26
DELPHS 26-69
DELTA
   element parameter 26-10 , 26-12 , 26-18 , 26-24 , 26-28 , 26-58 , 29-10
   internal timestep 9-43 , 11-20
       See also timestep
DELVTO model parameter 13-9
demo files
   2n2222 BJTs transistor characterization 31-32
   2n3330 JFETs transistor characterization 31-32
   A2D 31-29 , 31-30
   AC
      analysis 31-26
      resonance analysis 31-35
   acl gate 31-27
   A/D flash converter 31-30
   adders
      72-transistor two-bit 31-28
      BJT NAND gate two-bit 31-27
      BJT two-bit 31-26
      D2A 31-29
      MOS two-bit 31-27
      NAND gate four-bit binary 31-26
   air core transformer 31-35
   algebraic
      output variables 31-26
      parameters 31-26
      transmission lines 31-39
   .ALTER statement 31-26
   AM source 31-38
   amplifier 31-29
   amplitude modulator 31-27
   analog 31-28
   AND gate 31-27
   automatic model selection program 31-36
   behavioral applications 31-27 - 31-28
   behavioral models 31-28
      diode 31-27
      D-latch 31-27
      filter 31-26
      NAND gate 31-27
      ring oscillator 31-28
      triode 31-28
      voltage to frequency converter 31-26
   benchmarks 31-28
   bisection
      pass-fail 31-28
      search 31-28 , 31-29
   BJTs
      analog circuit 31-28
      beta plot 31-29
      differential amplifier 31-26 , 31-29
      diodes 31-29
      ft plot 31-29
      gm, gpi plots 31-29
      photocurrent 31-38
      Schmidt trigger 31-26
      sense amplifier 31-26
   BSIM3 model, LEVEL=47 31-35
   capacitances, MOS models
      LEVEL=13 31-35
      LEVEL=2 31-35
      LEVEL=6 31-36
   cell characterization 31-26 , 31-27 , 31-29
   charge conservation, MOS models
      LEVEL=3 31-36
      LEVEL=6 31-36
   circuit optimization 31-29 - 31-30
   CMOS
      differential amplifier 31-26
      input buffer 31-29
      inverter macro 31-28
      I/O driver ground bounce 31-26 , 31-38
      output buffer 31-29
   coax transmission line 31-39
   crystal oscillator 31-26
   current controlled
      current source 31-28
      voltage source 31-28
   D2A 31-29
   DC analysis, MOS model LEVEL=34 31-36
   DDL 31-30 - 31-32
   delay 31-26 , 31-29
      versus fanout 31-29
   device optimization 31-32 - 31-33
   differential amplifier 31-26
   differentiator 31-27
   diffusion effects 31-27
   diode photocurrent 31-37
   D-latch 31-27
   E Element 31-27
   edge triggered flip-flop 31-27
   exponential source 31-38
   FFT
      AM source 31-33
      analysis 31-33 - 31-34
      Bartlett window 31-33
      Blackman window 31-33
      Blackman-Harris window 31-34
      data-driven transient analysis 31-34
      exponential source 31-33
      Gaussian window 31-34
      Hamming window 31-34
      Hanning window 31-34
      harmonic distortion 31-33
      high frequency detection 31-33
      intermodulation distortion 31-34
      Kaiser window 31-34
      modulated pulse source 31-34
      Monte Carlo, Gaussian distribution 31-34
      product of waveforms 31-34
      pulse source 31-34
      PWL 31-34
      rectangular window 31-34
      single-frequency FM source 31-34
      sinusoidal source 31-34
      small-signal distortion 31-33
      switched capacitor 31-34
      transient 31-34
         sweep 31-34
      window tests 31-34
   filter matching 31-30
   filters 31-34 - 31-35
      behavioral 31-26
      fifth-order
         elliptical switched capacitor 31-28
         low-pass 31-35
      fourth-order Butterworth 31-35
      Kerwin's circuit 31-35
      LCR bandpass 31-35
      matching lossy to ideal 31-30
      ninth-order low-pass 31-27 , 31-35
      switched capacitor low-pass 31-27
   FR-4 microstrip transmission line 31-35 , 31-38
   G Element 31-26 , 31-27
   GaAsFET amplifier 31-26
   gamma model LEVEL=6 31-36
   general applications 31-26 - 31-27
   ground bounce 31-26 , 31-38
   group time delay 31-26
   impact ionization plot 31-36
   input 31-26
   installation test 31-28
   integrator 31-27
   inverter 31-27 , 31-28
      characterization 31-26 , 31-29
      sweep 31-29
   IRF340 NMOS transistor characterization 31-32
   I-V
      and C-V plots, LEVEL=3 31-36
      plots
         MOSFETs model LEVEL=13 31-36
         SOSFET's model LEVEL=27 31-36
   JFETs photocurrent 31-38
   junction tunnel diode 31-29
   LCR circuit 31-29
   lumped
      MOS model 31-26
      transmission lines 31-35 , 31-39
   magnetic core transformer 31-35
   magnetics 31-35
   microstrip transmission lines 31-35 , 31-39
      coupled 31-39
      optimization 31-39
      series 31-39
   Monte Carlo
      analysis 31-27
         DC 31-27
      Gaussian distribution 31-27
      limit function 31-27
      uniform distribution 31-27
   MOS
      amplifier 31-29
      simulation 31-28
   MOSFETs 31-35 - 31-36
      sigma sweep 31-29
      sweep 31-26
   NAND gate 31-27 , 31-28
   NMOS E-mode model, LEVEL=8 31-38
   noise analysis 31-26
   op-amp 31-26 , 31-27
      characterization 31-30 - 31-32
      voltage follower 31-27 , 31-38
   optimization 31-27
      2n3947 Gummel model 31-33
      DC 31-33
      diode
         I-V and C-V 31-33
         temperature 31-33
      GaAs
         FET 31-33
            s-parameter 31-33
         JFETs 31-33
      group delay 31-29
      Hfe 31-33
      I-V 31-33
      JFETs 31-33
      LEVEL=2 model beta 31-32
      LEVEL=28 31-33
      MOS 31-33
         LEVEL=13 I-V 31-33
         LEVEL=2 I-V 31-33
         LEVEL=3 I-V 31-33
         LEVEL=6 I-V 31-33
      s-parameter 31-33
      speed, power, area 31-29
      width 31-29
   parameters 31-26
   PCI
      Monte Carlo analysis 31-36
      worst-case modeling 31-36
   peripheral component interconnect
       See PCI
   phase
      detector 31-27
      locked loop 31-27
   photocurrent 31-36 - 31-38
      GaAs device 31-38
   photolithographic effects 31-27
   piecewise linear source
       See demo files, PWL
   pll 31-27
   pole/zero analysis 31-26 , 31-35
   pulse source 31-38
   PWL 31-38
      CCCS 31-28
      CCVS 31-28
      switch element 31-28
      VCCS 31-27 , 31-28
      VCO 31-28
      VCVS 31-28
   radiation effects 31-36 - 31-38
      bipolar devices 31-36 - 31-37
      DC I-V, JFETs 31-38
      GaAs differential amplifier 31-38
      JFETs devices 31-37
      MOSFETs devices 31-37
      NMOS
         NAND 31-38
         voltage divider 31-38
   RC circuit optimization 31-30
   resistor temperature coefficients 31-30
   RG58/AU coax test 31-35
   ring oscillator 31-28
   Royer magnetic core oscillator 31-35
   Schmidt trigger 31-26
   sense amplifier 31-26
   series source coupled transmission lines 31-39
   setup
      characterization 31-29
      time search 31-28 , 31-29
   shunt terminated transmission lines 31-39
   silicon controlled rectifier 31-28
   sine wave sampling 31-27 , 31-28
   single-frequency FM source 31-38
   sinusoidal source 31-38
   skew models 31-27
   SNAP to HSPICE conversion 31-29
   sources 31-38
   s-parameters 31-29 , 31-35
      LEVEL=13 31-36
   sweep 31-26
   switch 31-27
      characterization 31-27
   switched capacitor 31-27 , 31-38
      RC circuit 31-28
   temperature effects
      LEVEL=13 31-36
      LEVEL=6 31-36
   timing analysis 31-28
   total radiation dose 31-37
   transient analysis 31-26
   transistor characterization 31-32
   transmission lines 31-38 - 31-39
   triode model 31-28
   tunnel diodes 31-28 , 31-29
   twinlead transmission line model 31-39
   U models 31-39
   unity gain frequency 31-29
   Viewsim
      A2D input 31-29
      D2A input 31-29
   voltage
      controlled
         current source 31-27 , 31-28
         oscillator 31-26 , 31-28
         resistor inverter 31-38
         voltage source 31-28
      follower 31-27
      to frequency converter 31-26
      variable capacitor 31-27
   waveform smoothing 31-28
   worst case skew model 31-27
depletion
   capacitance
      DCAP equation selector 15-5 , 16-3 , 17-6
      equations 15-26
   MOS devices 20-3
DERIVATIVE keyword 8-49
derivative, measuring 8-43
design
   high speed, problems and solutions 25-3
   name 3-53
   partitioning 25-7
   stability 29-2
   time, reducing 29-2
Design Architect
   with AvanLink B-8
Design Viewpoint Editor (DVE)
   with AvanLink B-8
deviation, average 13-3
device
   capacitor, equations 14-10
   characterization 3-50
   DDL 3-50
   inductor, equations 14-17
   models 14-1
DFT 28-1
DI control option 9-21 , 9-39 , 10-39 , 11-16 , 12-8
DIAGNOSTIC option 9-15
diagnostic tables 10-49 - 10-50
dialectric
   loss modeling 18-12
dielectric
   constant 14-7
   thickness, wire model parameters 14-5
differentiator, behavioral 26-55
diffusion
   capacitance equations 15-26
   layer process parameters, MOSFETs LEVEL 13 21-106
DIFSIZ optimization parameters 13-42
digital
   files 5-50 , 26-31
   input 5-50
   vector file 5-60
DIM2
   distortion measure 12-9
   parameter 8-35
DIM3
   distortion measure 12-9
   parameter 8-35
diodes
   barrier 15-1
   breakdown example 5-41
   capacitance 15-25
      calculations 15-5
      equations 15-25 , 20-46
         depletion capacitance 15-26
         diffusion capacitance 15-26
         LEVEL 3 metal 15-27
         LEVEL 3 poly 15-27
         temperature 20-106
      Fowler-Nordheim 15-49
   CMI_DiodeEval 23-27
   conductance 15-17
   control options 15-4
   convergence problems 15-5
   current 15-16
      flow 8-24
   DC parameters 17-15
   elements
      template listings 8-58
   equations 15-22 - 15-32
      example 5-40
      Fowler-Nordheim diodes 15-49
   equivalent circuits 15-17 , 15-17 - 15-18
   EXPLI 9-19
   Fowler-Nordheim 15-3 , 15-48
      equations 15-49
   junction 15-1
      DC equations 15-23
      equations 15-22
      geometric 15-3
      model 15-7
         capacitance parameters (table) 15-12
         DC parameters (table) 15-9
      parameters 15-8
      periphery 4-13
      temperature 15-19
         parameters 15-19
   Junction Cap Model 15-33
   metal model capacitance parameters (table) 15-13
   models 3-30 , D-10
      define 15-16
      levels 15-4
      names 4-12
      noise parameters (table) 15-13
      regions 15-23
      statements 15-4
      using 15-1
      variables (table) 15-22
   MOSFETs 20-9
      capacitance equations 20-46
      equations 20-45
      model selector 20-9
      models 20-9 , 20-26
      resistance temperature 20-111
   noise equations 15-28
   nongeometric junction 15-3
   nonvolatile memory 15-1
   poly model capacitance parameters (table) 15-13
   polysilicon capacitor length 4-13
   power dissipation 8-26
   scaling
      options 15-4
      parameters 15-14 - 15-16
   Schottky, barrier 15-1
   series resistance units 15-11
   temperature
      compensation equations 15-28
      effects 15-19
      equations
         breakdown voltage 15-29
         contact potential 15-30
         energy gap 15-28
         grading coefficient 15-32
         junction capacitance 15-31
         leakage current 15-29
         resistance 15-32
         transit time 15-29
   types 15-3
   Zener 15-1 , 15-4
    See also junction diodes
directories
   installation directory 3-50
   tmp 1-12
DIS 26-69
Discrete Fourier Transform 28-1
.DISTO statement 12-9 , 12-10
distortion
   analysis 8-35 , 12-9
   measures 12-9
DLAT model parameter 20-30
DLEV model parameter C-13 , C-14 , C-21 , C-24 , C-28
DNB model parameter 20-28
document conventions iv
documentation
   FAQ A-4
documentation issues iv
dollar sign ($) comment delimiter 3-9
drain current equation, MOSFETs LEVEL 47 22-15
drain-to-source current, convergence error tolerance 9-20 , 10-37
DTA model parameter 15-35
DTEMP
   element parameter 13-5
   model parameter 13-5 , 13-6 , 31-18
DV
   calculation 9-30 , 10-39
   option 9-32 , 10-24 , 10-42
DVDT
   algorithm 9-43 , 9-46 , 11-15 , 11-18 , 11-29 , 11-33
   option 9-44 , 9-48 , 11-12 , 11-13 , 11-33 , 11-34
      timestep control 11-26 , 11-35
DVTR option 9-47 , 11-21
DW model parameter 20-30
dynamic timestep algorithm 11-34

E

E Elements 26-6 , 26-11 , 29-26 - 29-33
   applications 26-6
   controlling voltage 26-14
   data
      points 26-13
      sampler application 26-63
   element
      name 26-12
      value multiplier 26-13
   gate type 26-12
   initial conditions 26-12
   integrator application 26-54
   Laplace transform 29-4
   maximum voltage 26-13
   minimum voltage 26-13
   NAND gate 26-31
   parameters 26-12
      value multiplier 29-11
   polynomial
      coefficients 26-13
      dimension 26-13
   SCALE parameter 29-37
   temperature coefficients 26-13
   time delay keyword 26-13
   transformer application 26-57
   triode application 26-61
   turns ratio 26-12
   voltage gain 26-12
E elements
   syntax statements 5-29
Early voltage 21-5
Ebers-Moll model 16-1 , 16-5
ECL
   circuits 16-2
   devices 16-2
effective capacitance
   calculation 14-10
effective channel length, MOSFETs
   equations
      LEVEL 1 21-5
      LEVEL 13 21-112
      LEVEL 28 21-156
      LEVEL 39 21-189
      LEVEL 49 22-49 , 22-52
      LEVEL 5 21-38
      LEVEL 6 21-61
      LEVEL 8 21-94
   parameters
      LEVEL 1 21-3
      LEVEL 2 21-8 - 21-9
      LEVEL 3 21-20 , 21-24
      LEVEL 38 21-165
      LEVEL 5 21-35
      LEVEL 8 21-90
      LEVELs 6, 7 21-54 - 21-55
effective channel width, MOSFETs
   equations
      LEVEL 1 21-5
      LEVEL 13 21-112
      LEVEL 2 21-12
      LEVEL 28 21-156
      LEVEL 3 21-24
      LEVEL 39 21-189
      LEVEL 49 22-49 , 22-52
      LEVEL 5 21-38
      LEVEL 6 21-61
   parameters
      LEVEL 1 21-3
      LEVEL 2 21-8
      LEVEL 3 21-20 - 21-21
      LEVEL 38 21-165
      LEVEL 5 21-35
      LEVEL 8 21-90 - 21-91 , 21-94
effective mobility
   MOSFETs, equations
      LEVEL 28 21-157
      LEVEL 3 21-26
      LEVEL 6 21-75
      LEVEL 8 21-96
   parameters, LEVEL 6 21-75
EFPS option 20-11
EISA standard 25-33
electrical measurements
   simulating 31-20
ELEMENT
   statements 3-50
element
   active
      BJTs 4-14
      diodes 4-12
      JFETs 4-16
      MESFETs 4-16
      MOSFETs 4-18
   analog behavioral 26-53
   capacitors 14-9
   checking, suppression of 9-8
   current controlled 26-6
   IC parameter 10-9
   ideal 5-24
   independent source 5-2 , 5-7
   linear inductors 14-12
   markers, mutual inductors 4-10
   names 3-17
   OFF parameter 9-35 , 10-4 , 10-27
   parameters See element parameters 4-1
   passive
      capacitors 4-4
      inductor 4-6
      mutual inductor 4-9
      resistors 4-2
   statement, current output 8-22
   statements 3-10 , 20-4
      capacitor 14-9
      G Elements 26-16 - 26-22
      linear inductor 14-12
      op-amps 26-66
      transconductance
         Laplace 29-6
         pole/zero 29-7
      voltage gain
         Laplace 29-6
         pole/zero 29-7
   subcircuits 3-14
   temperature 13-6
   templates 8-35 - 8-58
      analysis 8-4
      BJTs 8-59
      capacitor 8-55
      current-controlled
         current source 8-57
         voltage source 8-57
      function 7-10
      independent
         current source 8-58
         voltage source 8-57
      inductor 8-55
      JFETs 8-61
      MOSFETs 8-62 , 22-128 , 22-144
      mutual inductor 8-56
      printout 20-62
      resistor 8-55
      saturable core
         element 8-65
         winding 8-65
      voltage-controlled
         current source 8-56
   transmission line 4-21 , 4-23 , 4-25
   voltage-controlled 26-6
      current source 5-24
      voltage source 5-24
ELEMENT parameters
   .ALTER blocks 3-41
element parameters
   BJTs 4-15
      model names 4-15
      node names 4-15
   capacitors 4-5 - 4-6 , 14-9 - 14-11
   DELTA 26-10
   diodes 15-6
      AREA 15-14
      M 15-14
   DTEMP 13-5
   E Elements 26-12 - 26-14
   F Elements 26-28 - 26-29
   G and E Elements 29-10 - 29-11
   G Elements 26-18 - 26-21
   H Elements 26-23 - 26-25
   IBIS buffers 4-27
   independent sources 5-2 - 5-3
      data driven PWL function 5-18
      PULSE function 5-7 , 5-10 , 5-13 , 5-15
      SFFM function 5-20
   inductors 4-7 - 4-8
      coefficients 4-8
   JFETs and MESFETs 4-16 - 4-17
   linear inductors 4-7
   M 15-14
   MOSFETs 4-18 - 4-20
      GEO 20-42
   mutual inductors, Kxxx 4-9
   POLY 26-7
   PWL
      PV 5-19
      R 5-16
      TIME 5-19
   range limits 22-52
   resistors 4-2 - 4-3
      DTEMP 4-3
   scaling 20-12
   transmission lines
      T Element 4-24
      U Element 4-25
      W Element 4-21 , 4-21 - 4-22
   U Elements C-50 - C-51
element statements
   BJT 16-20
   independent sources 5-2
elements
   templates
      MOSFET 22-157
ELEV model parameter C-7 , C-13 , C-14
Elmore delay 29-33
Empirical model 21-19
   equations 21-22
   example 21-30
enable (digital vector file) 5-72
encrypted data E-2
encryption
   file organization E-6
   FREELIB keyword E-7
   guidelines E-5
   permit file changes E-7
   semicolon bug E-5
Encryption structure example E-13
Encryption, 8-byte key E-9
.END statement
   for multiple HSPICE runs 3-45
   in libraries 3-34
   location 3-45
   missing 3-2
   with .ALTER 3-42
ENDDATA keyword 3-23 , 3-25 , 3-27
.ENDL statement 3-32 , 3-33
.ENDS statement 3-14
energy gap temperature equations
   BJTs 16-42
   JFETs and MESFETs 17-41
   MOSFETs 20-105
environment variables
   DDLPATH 3-51 , 31-20
   FAQ A-6
.EOM statement 3-14
EPFL-EKV MOSFETs model 22-85
epitaxial
   charge 16-52
   current source 16-51
EPSMIN option 9-11 , 29-20
equations
   ACM parameters 17-22
   BJTs
      DC models 16-29
      noise 16-40
      parasitic resistor temperature 16-49
      temperature 16-42 , 16-44
   BSIM LEVEL 13 21-112
   capacitance
      depletion 15-26
      diffusion 15-26
      diode 15-25
      effective 14-10
      metal and poly 15-27
      MOS diode 20-106
      MOSFETs 20-46
      overlap 20-73
      temperature 14-11 , 16-46
   capacitor 17-6
      device 14-9 , 14-10
   DC
      JFETs and MESFETs 17-31
      junction 15-23
   device
      capacitor 14-10
      inductor 14-17
   diodes
      capacitance 15-25 , 20-46
      Fowler-Nordheim 15-49
      junction 15-22
      MOSFETs 20-45
   error 8-52
   evaluation 8-45
   Frohman-Bentchkowski 21-77
   impact ionization 20-53
   inductor
      device 14-12 , 14-17
      temperature 14-17
   MOSFET models
      LEVEL 61 22-178
      LEVEL 62 22-186
   MOSFETs
      channel length modulation 20-111
      diode 20-45
         resistance 20-111
      impact ionization 20-53
      mobility temperature 20-111
      model parameters 20-51
      models
         BSIM2 21-186
         BSIM3 22-10
            Leff/Weff 22-9
         Cypress 21-169
         Empirical 21-22
         EPFL-EKV 22-92 , 22-107
            NQS 22-106
         HP a-Si TFT 21-211
         IDS
            LEVEL 5 21-37 , 21-43
            LEVEL 6 21-60 , 21-71
            LEVEL 8 21-93
         LEVELs 49 and 53 22-52
         modified BSIM LEVEL 28 21-155
         quasi-static 22-103
         Schichman-Hodges 21-5 , 21-11
      noise 20-99
      surface potential temperature 20-109
      temperature 20-105
      threshold voltage 20-110
      voltage 20-50
   noise 17-35 , 20-99
      BJTs 16-40
      junction diode 15-28
      MOSFETs LEVEL 55 22-107
   Normal Field 21-78
   resistor
      device 14-2
      model 14-5
      noise 14-7
      temperature 14-8
   Star-Hspice Δ L 21-85
   substrate current 16-31
   temperature
      BJTs 16-44
         parasitic resistor 16-49
      capacitance 14-11 , 16-46
      compensation 15-28 , 16-42
      energy gap 20-105
      inductor 14-17
      JFETs and MESFETs 17-38
      MOS diode capacitance 20-106
      MOSFETs 20-105
      saturation current 20-106
   transmission lines 18-3
   variable
      definitions 15-22
      names 16-25
      names and constants 17-11
   voltage 20-50
   Wang's 21-84
   wire
      capacitance 14-6
      resistance 14-5
equivalent
   circuit
      BJTs 16-21
      JFETs 17-7 , 17-8
      MESFETs 17-7
      MOSFETs 20-20 , 20-22
         AC analysis 20-24
         AC noise analysis 20-25
         transient analysis 20-23
   variables and constants 20-20
ERR function 8-51 , 8-52
ERR1
   function 8-51 , 8-53
   keyword 13-37
ERR2 function 8-51 , 8-53
ERR3 function 8-51 , 8-53
errors
   bulk node not specified 14-7
   cannot open
      input file 3-58
      output spool file 8-18
   control options A-27
   current exceeding MAXAMP 9-39 , 11-17
   DC 10-45
   digital file has blank first line 5-50
   environment variables A-6
   file open 1-13
   functions 8-51 - 8-53
   input A-12 , A-32
   installation A-13
   internal timestep too small 9-34 , 9-39 , 9-46 , 9-48 , 10-5 , 10-25 , 10-53 , 11-3 , 11-12 , 11-13 , 11-23
   licensing A-15
   messages 19-46 , A-7
   missing .END statement 3-2
   models A-20
   negative slope for magnetization level 14-19
   netlist A-27
   no DC path to ground 10-47
   no input data 1-12
   optimization goal 8-40
   parameter name conflict 8-38
   PC A-23
   reference to undefined inductor 14-18
   special characters in input 3-3
   system resource inaccessible 8-18
   timestep control error in transmission lines C-61
   tolerances
      ABSMOS 9-20 , 10-37
      branch current 9-20 , 9-21 , 10-22 , 10-37
      optimization by bisection 30-8
      pole/zero analysis 9-36 , 10-32
      relative change 9-22 , 9-40 , 10-41 , 11-18
      RELMOS 9-20 , 10-37
      voltage 9-22 , 9-23 , 9-40 , 10-41 , 11-18
EXA model parameter 20-28
example
   AC analysis
      Hspice vs. SPICE methods 8-31
      RC network 2-2
   capacitance, MOSFETs 20-64
   cascoding 20-55
   .DATA
      inner sweep 3-24
      outer sweep
   digital vector file 5-62
   experiments 1-8
   .FFT statement 11-41
   field solver 18-45
   gate capacitance 20-64
   Hspice vs .SPICE methods
      AC analysis 8-31
   hysteresis 14-23
   input buffer 19-42
   .MODEL CARDS NMOS model 22-53
   Monte Carlo 13-18 , 13-26
   MOSFETs
      BSIM LEVEL 13 21-121
      data fitting 21-227
      Empirical 21-30
      gate capacitance 20-64
      IDS LEVEL 5 21-50
      IDS LEVEL 7 21-66 , 21-68
   network analysis, bipolar transistor 12-21
   optimization 13-44
   .OPTIONS SEARCH 3-36
   output buffer 19-42
   parameter extraction 14-24
   PMOS model 22-55
   S parameter 6-8
   simulation PCI 25-46
   subcircuit 3-15
      MULTI model 3-15
   subcircuit test 3-13
   transient analysis
      inverter 2-7
      RC network 2-5
   transmission line 19-42 , C-8
   worst case 13-26
excess phase 16-39
EXD model parameter 20-28
EXJ model parameter 20-28
EXP model parameter 20-28
EXP source function
   fall time
      constant 5-13
      delay 5-13
   initial value 5-13
   pulsed value 5-13
   rise time
      constant 5-13
      delay 5-13
exp(x) function 7-10
experiment 1-8
experimental methods
   using Star-Hspice 1-8
EXPLI option 9-19
EXPMAX option 9-11
exponential
   function 7-10
   source function 5-13
expressions
   algebraic 7-8
EXS model parameter 20-28
external data files 3-7 , 3-22
EXTRAPOLATION
   element parameter 29-10

F

F Elements 26-6 , 26-27
   applications 26-7
   controlling voltage 26-30
   current gain 26-28
   data points 26-29
   gate type 26-28
   initial conditions 26-28
   maximum current 26-28
   minimum current 26-29
   multiply parameter 26-28
   name 26-28
   parameters 26-28
   polynomial
      coefficients 26-29
      dimension 26-29
   temperature coefficients 26-29
   time delay keyword 26-29
   value multiplier 26-29
F elements
   syntax statements 5-46
FALL keyword 8-41
fall time
   example 24-9
   EXP source function 5-13
   simulation example 24-2
fanout, plotting 24-5
FAQ
   analysis A-2
   control options A-27
   environment variables A-6
   error messages A-7
   field solver A-34
   input A-12
   installation A-13
   known limitations A-17
   licensing A-15
   manuals A-4
   models A-20
   MS Windows/PC A-23
   netlist A-27
   output A-32
   W Element A-34
   waveform viewing A-35
Fast Fourier Transform
    See FFT
FAST option 9-42 , 11-17 , 11-25
FC model parameter 20-28
ferromagnetic core 14-12
   model 14-19
FFT
   analysis
      alfa control parameter 28-8
      example
         AM modulation 28-13
         modulator/demodulator 28-16
         test circuit 28-24
      frequency
         maximum 28-8
         minimum 28-8
         of interest 28-10
         range 28-10 , 28-11
         specification 28-8
      harmonic distortion 28-16
      number of points 28-7
      output 11-44
         magnitude format 28-7
      results 28-10 - 28-12
      spectral leakage 28-16
      start point 28-7
      statement syntax 28-7 - 28-9
      stop point 28-7
      window type 28-8
   output 28-10
   windows 28-3 - 28-5
      Bartlett 28-4
      Blackman 28-4
      Blackman-Harris 28-4
      Gaussian 28-4
      Hamming 28-4
      Hanning 28-4
      Kaiser-Bessel 28-4
      rectangular 28-4
.FFT statement 28-1 , 28-7
field effect transistor 20-16
   geometry 20-16
   models D-12
    See also MOSFETs, JFETs
field programmable gate arrays 25-22
field solver
   accuracy updates 18-12
   examples 18-45
   FAQ A-34
   statement syntax 18-36
   W Element 18-24
FIL keyword 3-22
file descriptors limit 8-18
files
   .a2d 3-55 , 3-57 , 5-50
   AC analysis
      measurement 3-57
      results 3-57
   .ac# 3-55
   column lamination 3-28
   concatenated data files 3-26
   .d2a 5-50
   DC analysis
      measurements 3-56
      results 3-56
   design.ac0 24-1
   design.mt0 24-1
   design.sw0 24-1
   external data 3-7 , 3-21
   filenames 3-22
   .ft# 3-55 , 3-57 , 28-11
   .gr# 3-55
   graph data 1-9 , 3-57
   hspice.ini 9-12
      creation 3-51
   .ic 3-55 , 10-4
   include files 3-6 , 3-29 , 3-35
   including 3-54
   initialization 3-54
   input 1-9
      file name 3-59
   limit on number 8-18
   .lis 3-55
   .ma# 3-55
   .MEASURE output 24-1
   .ms# 3-55
   .mt# 3-55
   multiple simulation runs 3-45
   names 3-53 , 3-59 - 3-61
   output
      listing 3-56
      names 3-61
      status 3-57
      version number 3-60
   .pa# 3-55
   scratch files 1-12
   .st# 3-55
   subcircuit node cross-listing 3-57
   .sw# 3-55
   .tr# 3-55
   transient analysis
      measurement 3-56
      results 3-56
   transition data 26-4
filing a documentation bug iv
filters
   30 degree phase shift 29-17
   active low-pass 27-15
   band reject 29-12
   low-pass 29-14
   pole/zero analysis
      Butterworth 27-10
      high-pass 27-10
      low-pass 27-5 , 27-15
   transfer functions 29-31
FIND keyword 8-43
flicker noise 20-99
floating point overflow
   CONVERGE setting 9-29 , 10-38
   setting GMINDC 9-33 , 10-40
Fluke-Mosaid model 20-5
FMAX
   .FFT parameter 28-8
   option 9-35 , 10-31 , 27-4
FMIN .FFT parameter 28-8
FORMAT .FFT parameter 28-7
Fourier
   analysis 11-37
   coefficients 11-39
   equation 11-39
   integral 29-5
   transfer function H(f) 29-5
   transform 29-5
.FOURIER statement 11-38
Fowler-Nordheim diodes 15-3 , 15-6
   capacitances 15-49
   equations 15-49
   model parameters 15-48
   using 15-48
FPGA's 25-22
FR1 model parameter C-36
FREELIB keyword E-7
FREQ
   element parameter 29-10
   function
      transconductance element statement 29-8
      voltage gain element statement 29-9
   keyword 29-5
   model parameter 8-13 , 26-69
frequency
   analysis 28-1
      Nyquist 29-11
      poles and zeros 29-11
   complex 29-4 , 29-20
   critical 29-5
   domain to time domain 29-1
   domain, transfer function 29-20
   low model parameters 16-5
   maximum 29-6
      frequency analysis 29-11
      setting 9-35 , 10-31
   ratio 12-10
   resolution 29-6
      Fourier analysis 29-6
      frequency analysis 29-10
   response 29-4
      analysis 29-3
      table 29-8 , 29-10
         parameters 29-9
   setting scale 9-35 , 10-31
   sweep 12-6
   table 29-3
   variable 7-11
   weighing functions 28-3
Frequency Table Model 6-4
frequency-domain model 6-2
Frohman-Bentchkowski equations 21-77
FROM
   .FFT parameter 28-7
   keyword 8-52
FS
   keyword 12-13
   option 9-44 , 9-46 , 11-21 , 11-23 , 11-35
FSCAL option 9-35 , 9-37 , 10-31 , 10-33 , 27-4
FT option 9-44 , 9-46 , 11-21 , 11-23 , 11-35
   timestep control 11-35
.ft# file 3-55 , 3-57 , 28-11
functions
   A2D 5-50 , 26-4
   bisection 30-1
   built-in 7-9 - 7-11
   D2A 5-50 , 26-4
   DERIVATIVE 8-48
   ERR 8-51
   INTEG 8-48
   LAPLACE 27-1 , 29-2 , 29-6
   NPWL 5-35
   OPTIMIZE 26-3
   POLE 27-1 , 29-2 , 29-7
   PPWL 5-36
   redefining 7-11
   table 7-9
   user-defined 7-11
    See also independent sources
FV function value 26-7

G

G Elements 26-6 , 26-16 , 29-26 - 29-31
   amplitude modulator application 26-62
   AND gate 26-31
   applications 26-6
   controlling voltages 26-19 , 26-21
   curve smoothing 26-20
   data points 26-19
   DELTA parameter 26-58
   element value multiplier 26-20
   gate type 26-19
   initial conditions 26-19
   Laplace transform 29-4
   maximum
      current 26-19
      resistance 26-19
   minimum
      current 26-19
      resistance 26-19
   multiply parameter 26-19 , 29-11
   names 26-18
   parameter value multiplier 29-11
   polynomial
      coefficients 26-19
      dimension 26-20
   temperature coefficients 26-20
   time delay keyword 26-20
   transconductance 26-20
   triode application 26-61
   tunnel diode application 26-58
   voltage to resistance factor 26-20
G elements
   syntax statements 5-34
GaAsFET model DC optimization 13-67
gain, calculating 8-31
gate
   capacitance 20-94
      AMI 20-94
      charge sharing coefficient 20-72
      equations, JFETs and MESFETs 17-25 - 17-30
      length/width 20-97
      model (CAPOP=39) 21-194
      modeling 21-225
      MOSFETs
         example 20-64
         LEVEL 39 21-192 , 21-197
      parameters
         JFETs 17-17 - 17-18
         MOSFETs 20-69
            models 20-57
      plotting 20-66
      SPICE 20-74
      temperature equations, JFETs and MESFETs 17-42
   diode DC parameters, JFETs 17-15 - 17-16
GAUSS
   FFT analysis
      keyword 28-8
      window 28-4 , 28-28
   functions 13-20
   keyword 13-16
   parameter distribution 13-14
GBW model parameter 26-69
GEAR algorithm 9-48 , 11-13 , 11-29
GE-CRD Franz model 20-5
GE-Intersil model 20-6
GENK option 9-19
geometric model parameter 16-6
geometry
   ACM 17-22
   JFETs and MESFETs parameters 17-7
   MOSFETs model parameters 20-30
   SCALE 15-5
   scaling 20-12
   SCALM 15-5
   substrate diode 16-28
   transistor field effect 20-16
getting customer support vi
global
   node names 3-20
   parameters 7-14
   scaling 20-12
      overriding 17-7
         in models 15-4
.GLOBAL statement 3-19
GMAX option 9-33 , 10-40
GMIN 15-5 , 16-2
   option 9-39 , 10-54 , 11-21 , 17-6 , 20-11
      stepping 9-33 , 10-40
GMINDC 15-5 , 16-2
   option 9-33 , 10-40 , 10-42 , 10-54 , 20-11 , 20-26
      JFETs and MESFETs conductance 17-6
GND node 3-17
GOAL keyword 8-46 , 13-37
golden parser (IBIS) 19-1
.gr# file 3-55 , 3-57
   maximum version number 8-11
GRAD optimization parameter 13-42
gradient data, printing 9-8
GRAMP
   calculation 9-30 , 10-39
   conductance option 17-6
   option 9-33 , 10-24 , 10-40 , 10-42 , 10-46
graph data
   file 1-9
   Viewlogic format 9-11
    See also .gr# file
.GRAPH statement 8-2 , 31-7
   simulation results 8-10 , 8-19
ground
   bounce 25-24
   node name 3-17
   plane, transmission lines C-5
group delay, calculating 9-51 , 12-8
Grove-Frohman model 20-4
GSCAL
   multiplier 9-36 , 10-32
   option 9-35 , 10-31 , 27-4
GSHUNT option 9-34 , 9-39 , 10-25 , 11-12
Gummel-Poon model 16-1 , 16-50
Gxxx element parameters 26-18

H

H Elements 26-6 , 26-23
   applications 26-6
   controlling voltage 26-25
   data points 26-24
   element
      name 26-24
      value multiplier 26-25
   gate type 26-24
   initial conditions 26-24
   maximum current 26-24
   minimum current 26-24
   polynomial
      coefficients 26-25
      dimension 26-25
   SCR application 26-60
   temperature coefficients 26-25
   time delay keyword 26-25
   transresistance 26-25
H elements
   syntax statements 5-42
H parameters 12-21
H9007 option 9-15
HAMM FFT analysis keyword 28-8
Hamming FFT analysis window 28-4 , 28-27
HANN FFT analysis keyword 28-8
Hanning FFT analysis window 28-4 , 28-26
harmonic distortion 12-9 , 28-1
HARRIS FFT analysis keyword 28-8
HD2
   distortion measure 12-9
   parameter 8-35
HD3
   distortion measure 12-9
   parameter 8-35
HDIF model parameter 20-30
hertz variable 7-11
HGP model parameter C-15 , C-24 , C-26 , C-28
HiCUM model
   BJT
      parameters 16-95
HiCUM model, BJT 16-93
hierarchical designs, flattened 3-6
hold time 30-4
HP a-Si TFT model 21-207
   equations 21-211
   topology 21-217
HSPICE
   ground for transmission lines C-18
   installation directory 3-50
   integration method C-20
   job statistics report 8-16 - 8-18
   model enhancements 21-218
   output, redirecting 3-61
   starting 1-12
   version
      95.3 compatibility 11-35
      H9007 compatibility 9-15
      specifying 3-59
   VERSION parameter 3-31 , 21-111
hspice command 3-58 - 3-62
   arguments 3-59
Hspice junction diode model 22-24
hspice.ini file 9-12
   creating 3-51
HT model parameter C-14 , C-24
HT1 model parameter C-24
hybrid (H) parameters 8-29
hysteresis, Jiles-Atherton example 14-23

I

IB model parameter 26-69
IBIS
   buffers 4-27
   conventions 19-3
   differential pins 19-36
   enhancements 19-44
   keywords
      optional 19-26
      required 19-26
   limitations/restrictions 19-5
   models 19-1
   references 19-49
   terminology 19-4
IBOS model parameter 26-70
IC
   element parameter 10-9 , 26-12 , 26-19 , 26-24 , 26-28
   keyword 10-12
   parameter 10-9
.ic file 3-55 , 10-4
.IC statement 10-3 , 10-4 , 10-9 , 27-3
   balancing input nodes 26-66
   from .SAVE 10-12
ICSWEEP option 9-34 , 10-25
ideal
   current sources 10-46
   delay elements 26-6 , 26-7
      DELMAX setting 11-26
   op-amp 5-29 , 5-32 , 26-6 , 26-11 , 26-13 , 26-14
   transformer 5-30 , 5-33 , 26-6 , 26-12 , 26-15 , 26-57
   transmission line C-6 , C-10
idelay (digital vector file) 5-73
IDS
   Cypress depletion model 20-6
   equations
      LEVEL 1 21-5
      LEVEL 13 21-113
      LEVEL 2 21-11
      LEVEL 3 21-22
      LEVEL 38 21-169
      LEVEL 5 21-37
      LEVEL 6 21-60 , 21-71
      LEVEL 8 21-93
   LEVEL 38 Cypress model 21-162
   LEVEL 5
      equations 21-43
      example 21-50
      model 21-34
   LEVEL 6
      equations 21-60 , 21-71
      example 21-66 , 21-68
   LEVEL 7 model 21-88
   LEVEL 8
      equations 21-93
      model 21-89
IGNOR keyword 8-52
IKF model parameter 16-2
IKR model parameter 16-2
imaginary
   part of AC voltage 8-31
   vs. real component ratio 10-32
imaginary vs. real component ratio 9-36
IMAX option 9-45 , 9-47 , 11-21 , 11-33
   default 11-33
IMIN option 9-45 , 9-48 , 11-22 , 11-33
   default 11-33
impact ionization
   BSIM2 21-197
   MOSFETs 20-53
      equations 20-23 , 20-53
      LEVEL 39 21-197
      LEVEL 55 22-90
impedance C-72
   AC 8-34
   versus time 25-9
   Z parameters 8-29
impulse response h(t) 29-5
inactive devices
    See latent devices
.inc file encryption E-12
include files 3-29 , 3-35 , 3-54
.INCLUDE statement 3-6 , 3-29 , 3-51 , 3-52
   and .ALTER blocks 3-42
independent sources
   AC 5-5
      magnitude parameter 5-3
      phase parameter 5-3
   AM function 5-22
   current
      element template listings 8-58
      source name 5-3
   data driven PWL function 5-18
   DC 5-5
      source value parameter 5-3
   elements
      parameters 5-2
      statements 5-2
   EXP function 5-13
   functions 5-7
   mixed types 5-6
   PULSE function 5-7
   PWL function 5-15
   SFFM function 5-20
   SIN function 5-10
   transient 5-5
      source function 5-3
   types 5-7
   voltage
      element template listings 8-57
      source name 5-3
    See also sources
individual element temperature 13-5
inductance C-75
   matrixes C-52
   mutual 14-18
   scale 9-36 , 10-32
   temperature equation 14-17
inductors
   core models 14-12
   coupling 14-18
   current flow 8-23
   device
      equations 14-17
      model 14-12
   element 4-6
      template listings 8-55
   GENK 9-19
   KLIM 9-19
   linear 14-12
      branch relations 14-18
   mutual models 3-30
   node names 4-7
   temperature, equation 14-17
INGOLD option 9-6 , 9-7
initial conditions 10-3
   file 3-54
   saving and reusing 9-34 , 10-25
   statement 10-9
   transient 11-7
initialization 9-35 , 10-3 , 10-4 , 10-27
   file 3-54
   saved operating point 10-11
inline data 3-23
inner sweep 3-25
INOISE parameter 8-35
input
   admittance 8-34
   buffer 19-6 , 19-7
      ECL 19-19
      example 19-42
   data
      adding library data 3-42
      column laminated 3-28
      concatenated data files 3-26
      deleting library data 3-43
      external, with .DATA statement 3-22
      filenames on networks 3-29
      for data driven analysis 3-21
      formats 3-24 , 3-27 , 3-28
      include files 3-29
      printing 9-7
      suppressing printout 9-7
   FAQ A-12
   files
      character case 3-3
      compression 3-2
      configuration file 3-54
      control characters 3-3
      DC operating point 3-54
      demonstration 31-26
      initialization 3-54
      names 3-53 , 3-59
      netlist 3-2
      structure 3-6
      table of components 3-7
      unprintable characters 3-3
   impedance 8-34
   netlist
      file 1-9
         composition 3-9
         delimiters 3-4
         .END statement requirement 3-45
         expressions 3-5
         format 3-2
         guidelines 3-2
         hierarchy paths 3-5
         instance names 3-4
         names 3-3
         nodes 3-4
         numbers 3-5
         parameters 3-5
         schematic vetlists 3-6
         sections and chapter references 3-7
         structure 3-6
          See also input files
      simulation F-2
input/output
   cell modeling 31-23
   digital vector file 5-70
   drivers 25-18
   ECL buffer 19-23
   open
      drain buffer 19-18
      sink buffer 19-18
      source buffers 19-18
installation
   FAQ A-13
installation directory $installdir 3-50
insulation breakdown devices 15-48
int(x) function 7-10
INTEG keyword 8-47 , 8-48
integer function 7-10
integration
   algorithms 11-29 , C-43 , C-61
   backward Euler method 9-48 , 11-14
   method C-20
   order of 9-48 , 11-14
integrator, behavioral 26-53
Intel PCI Speedway models D-15
interconnect
   analyzing 25-2
   simulation C-10
    See also transmission lines, wires
interfaces
   Analog Artist 9-11
   AvanWaves 8-2
   Mentor 9-12
   MSPICE 9-12
   variables 23-18
   ZUKEN 9-13
intermodulation distortion 12-9
internal
   nodes, referencing 3-18
   routines 23-38
INTERP option 9-50 , 11-12
INTERPOLATION
   element parameter 29-10
interstage gain 8-31
intrinsic model parameters
   limits 22-109
inverse Laplace transform 29-33
inverter
   analysis, transient 2-7
   circuit, MOS 2-7
   gate 26-15
   lookup table 26-43
ion-implanted devices 20-3
IS model parameter 20-27
ISA standard 25-33
ISC model parameter 26-70
isoplanar
   MOSFETs
      construction 20-18
      width cut 20-19
   silicon gate transistor 20-17
ISPICE LEVEL 6 model 21-72
iterations
   algorithm 11-31
   count algorithm 11-33
   extra 9-34 , 10-26
   limit 9-23 , 10-25
   maximum number of 9-46 , 11-23
   number 13-54
ITL1
   calculation 9-30 , 10-39
   option 9-23 , 10-25
ITL2 option 10-26
ITL3 option 9-45 , 11-22
ITL4 option 9-46 , 11-22
ITL5 option 9-46 , 11-23
ITLPZ option 9-42 , 10-31 , 27-4
ITROPT optimization parameter 13-42
ITRPRT option 9-50 , 11-13
I-V and C-V plotting demo 31-7

J

Jacobian data, printing 9-8
JFETs
   capacitance
      equations 17-6 , 17-25
      parameters 17-29
   CAPOP=2 model parameters 17-29
   control options 17-6
   convergence 17-6
   current convention 17-7
   current flow 8-24
   DC
      model
         equation selector 17-13
         LEVEL 1 parameters 17-19
         LEVEL 2 parameters 17-19 - 17-20
         LEVEL 3 parameters 17-21 - 17-22
      voltage equations 17-31
   element
      names 4-17
      template listings 8-61
   equivalent circuits 17-7 , 17-8
   gate
      capacitance parameters 17-17 - 17-18
      diode DC parameters 17-15 - 17-16
   length 4-17
   model
      constants 17-11
      names 17-13
      parameters 17-6 , 17-13 , 17-14
      specifying 17-3
      statements 17-13
      variables 17-11
   n-channel specification 17-13
   noise
      equations 17-35
      parameters 17-35
      summary printout 17-37
   output conductance 17-9
   overview 17-2
   p-channel specification 17-13
   power dissipation 8-27
   scaling 17-7
   temperature
      equations 17-38 , 17-41 - 17-44
      parameters 17-38 , 17-39
   TOM model parameters 17-46
   transconductance 17-8
   width 4-17
Jiles-Atherton
   example
      hysteresis 14-23
      parameter extraction 14-24
      varying parameters 14-20
   model 14-12 , 14-19
      examples 14-20
      parameters 14-16
JIS model parameter 26-70
JS model parameter 20-27
JSDBR model parameter 15-35
JSDGR model parameter 15-36
JSDSR model parameter 15-35
JSGBR model parameter 15-35
JSGGR model parameter 15-35 , 15-36
JSGSR model parameter 15-35
JSW model parameter 20-27
Juncap diode
   electrical variable 15-39
   internal variable 15-40
   leakage 15-44
Juncap diodes
   capacitance charge 15-38
   current voltage 15-37
   equations 15-38
   model parameters 15-35
JUNCAP model parameters 22-62
junction
   capacitance 16-6
   capacitor parameters 16-11
   DC 15-23
   diodes
      element parameters 15-6
      equations 15-22
      geometric 15-6
      line-to-line 18-8
      nongeometric 15-6
      parameters 15-6
      Silicon diffused 15-1
      temperature 15-19
   model
      parameters 15-8
      statement 15-7
   parameters
      MOSFETs LEVELs 49 and 53 22-44
      setting
         capacitance 15-12
         DC LEVEL 1 and 3 15-9
Junction Cap Model 15-33
Junction diode
   ON/OFF 15-41

K

K model parameters 14-20
KAISER FFT analysis keyword 28-8
Kaiser-Bessel FFT analysis window 28-4 , 28-6 , 28-29
KCLTEST 10-26
   option 9-21
KD model parameter C-15 , C-25 , C-26 , C-28
KD1 model parameter C-25
KD2 model parameter C-25
Kerwin's circuit, pole/zero analysis 27-8
keywords
   .AC statement parameters 12-5
   analysis statement syntax 13-39
   BART 28-8
   command syntax 30-8
   DATA statement parameters 3-21
   .DC statement parameters 10-15
   DTEMP 13-5
   ERR1 13-37
   .FFT statement parameters 28-7
   FREELIB E-7
   FREQ 29-5
   FS 12-13
   GOAL 13-37
   IBIS optional 19-26
   LAST 8-42 , 8-43 , 8-45
   .MEASUREMENT statement parameters 8-47
   .MODEL statement parameters 8-12
   MONTE 13-14
   optimization syntax 13-38
   PAR 7-8
   power output 8-26
   PP 8-46 , 8-47
   RECT 28-8
   source functions 5-2
   target syntax 8-42
   .TRAN statement parameters 11-5
   UNORM 28-7
   weight 8-47
KF model parameter 12-13
Kirchhoff's Current Law (KCL) test 9-21 , 10-26
KLIM option 9-19

L

L capacitor parameter 15-6
LAM keyword 3-22 , 3-29
lambda equations, MOSFETs LEVEL 6 21-61 , 21-63
laminated data 3-28
LAPLACE
   element parameter 29-11
   function 27-1 , 29-2 , 29-5 , 29-6 , 29-24 - 29-28
      modeling 29-20
      transconductance element statement 29-6
      voltage gain element statement 29-6
Laplace
   band-reject filter 29-12
   low-pass filter 29-14
   parameters 29-9
   transfer function 29-2 , 29-20
   transform 29-2 , 29-6 , 29-21 , 29-22
      frequency
         analysis 29-11
         response table 29-8
      function call 29-4
      inverse 29-33
      modeling 29-20
      POLE (pole/zero) function 29-28
LAST keyword 8-42 , 8-43 , 8-45
LATD model parameter 20-30
latency option 20-13
latent devices
   BYPASS option 9-42 , 11-11 , 11-16 , 20-13
   bypassing 20-13
   BYTOL option 9-42 , 11-16
   excluding 9-42 , 11-17
   MBYPASS option 9-42 , 11-16
   removing from simulation 9-42 , 11-16
   VNTOL option 9-42 , 11-16
Lattin-Jenkins-Grove model 20-5
layer stacks, transmission line 18-37
LC oscillator model 26-83
LD model parameter 20-30
LDAC parameter 20-98
LDIF model parameter 20-30
leadframe example 31-12
LENGTH model parameter 13-22
LENNAM option 9-6
LEVEL
   diode parameter 15-4
   element parameter 29-11
   model
      parameter C-13 , C-14
      selector 17-3
   optimization parameter 13-42
levels, MOSFETs models 20-3 , 20-4
Levenberg-Marquardt algorithm 13-53
LEVIN model parameter 26-70
LEVOUT model parameter 26-70
LG model parameter 15-35
.LIB
   call statement 3-32
   definition statement 3-33
      building libraries 3-33
   statement 3-6 , 3-52
      in .ALTER blocks 3-32 , 3-41
      nesting 3-33
      with .DEL LIB 3-42
      with multiple .ALTER statements 3-42
.lib file encryption E-11
libraries
   adding with .LIB 3-42
   ASIC cells 3-51
   AvanLink B-5
   building
      rules 3-34
      with .LIB definition 3-33
   configuring 7-17
   creating parameters 7-14
   DDL 3-50
      accessing 3-36
   defining macros 3-33
   deleting 3-42
   device D-1
   duplicated parameter names 7-14
   encryption E-1
   .END statement 3-34
   integrity 7-13
   listings D-5
   private 3-40
   protecting 3-40 , E-1
   search
      order 3-51
      path 3-51
   selecting 3-37
   subcircuits 3-52
   vendor 3-51
licesne issues, FAQ A-15
limit descriptors command 8-18
LIMIT keyword 13-17
limitations, known A-17
LIMPTS option 9-13
LIMTIM option 9-11
LIN keyword 10-16 , 11-6 , 12-6
linear
   region equations, MOSFETs LEVEL 47 22-14
   technology device models D-14
.lis file 3-55 , 3-56
LIST option 9-7
listing
   page width 8-14
   suppressing 3-40
LLEV model parameter C-13 , C-14
LM capacitor parameter 15-6
LMAX model parameter 1-5
LMIN model parameter 1-5
.LOAD statement 10-11
local
   parameters 7-14
   truncation error algorithm 9-41 , 9-48 , 11-13 , 11-19 , 11-33 , 11-34
      timestep 9-40 , 11-18
log(x) function 7-10
log10(x) function 7-10
logarithm function 7-10
lossless
   parameter combinations C-37
   transmission lines C-6
      model C-70
lossy
   transmission lines C-6 , C-11
      model C-71
   U model C-13
low-frequency large-signal characteristics
   using Ebers-Moll model 16-5
LP capacitor parameter 15-6
LRD model parameter 20-29
LRS model parameter 20-29
LS model parameter 15-35
LSCAL option 9-36 , 10-32 , 27-4
Lsim models, calibrating 24-1
lumped parameters C-19
LV 8-36
LV18 model parameter 31-7
LVLTIM option 9-41 , 9-46 , 9-48 , 9-49 , 11-13 , 11-14 , 11-18 , 11-19 , 11-27 , 11-33
   timestep control 11-35
LX 8-36
LX7 model parameter 31-7
LX8 model parameter 31-7
LX9 model parameter 31-7

M

M
   capacitor parameter 15-6
   element parameter 15-14 , 26-19 , 26-28 , 29-11
   multiplier parameter
      U and T Elements C-5
.ma# file 3-55 , 3-57
mA741 op-amp 26-76
.MACRO statement 3-12
macros
   defining with .LIB definition 3-33
   deleting library data 3-42
magnetic core 14-12
   element outputs 14-16
   models 3-30
      ferromagnetic core 14-19
      names 14-12
      parameters 14-14 , 14-16
      saturable core 14-12
      statement 14-12
   outputs (table) 14-16
magnitude
   AC voltage 8-31
   calculating 8-31
MANU model parameter 26-70
manufacturing tolerances 13-21
Marquardt scaling parameter 13-53
mask (digital vector file) 5-73
matrix
   calculations 9-23 , 10-26
   conductance 18-4
   minimum pivot values 9-25 , 10-29
   parameters 12-14
   properties 18-4
   resistance 18-4
   row/matrix ratio 9-25 , 10-29
   size limitation 9-25 , 10-28
MAX
   element parameter 26-13 , 26-19 , 26-24 , 26-28 , 29-11
   function 30-5
   keyword 8-47
   optimization parameter 13-42
max(x,y) function 7-10
MAXAMP option 9-22 , 9-39 , 10-26 , 11-17 , 12-8
MAXD model parameter C-15
MAXF
   element parameter 29-11
   parameter 29-6
MAXFLD keyword 12-14
maximum
   number size 9-11
   value, measuring 8-46
MAXORD option 9-48 , 11-14
Maxwell matrix C-34
MBYPAS option 20-11
MBYPASS option 9-42 , 9-43 , 11-16 , 11-17 , 20-13
mean, statistical 13-3
MEASDGT option 9-6 , 9-7
MEASFAIL option 9-50
measfail value 30-8
MEASOUT option 9-12
measure
   data output formatting 9-7
   parameter types 8-38
.MEASURE statement 8-2 , 8-3 , 8-38 , 9-7 , 9-12
   failure message 8-37
   parameters 7-7
   PCI modeling 25-41
   performance 8-3
   TDR files 25-9
Mentor interface 9-12
MENTOR option 9-12
MER keyword 3-22 , 3-27 , 3-29
MESFETs
   capacitance equations 17-6 , 17-25
   CAPOP=2 model parameters 17-29
   control options 17-6
   convergence 17-6
   DC
      model equation selector 17-13
      voltage equations 17-31
   element names 4-16
   equivalent circuits 17-7
   models
      constants 17-11
      names 17-13
      parameters 17-6 , 17-13 , 17-14
      specifying 17-3
      statements 17-13
      variables 17-11
   n-channel specification 17-13
   noise
      equations 17-35
      parameters 17-35
      summary printout 17-37
   overview 17-2
   p-channel specification 17-13
   scaling 17-7
   temperature
      equations 17-38 , 17-41 - 17-44
messages
   pivot change 9-25 , 9-27 , 10-28 , 10-31
    See also errors, warnings
Metaencrypt features E-9
Metaencrypt, character length restrictions E-6
metal and poly capacitance equations 15-27
metal contact 20-17
METHOD option 9-49 , 11-14
Meyer
   and Charge Conservation Model parameters 8-64
   capacitance
      modified 20-81
      parameters 20-71
   gate capacitances
      modified 20-77
   model 20-57
microstrip transmission line C-21
MIN
   element parameter 26-13 , 26-19 , 26-24 , 26-29
   keyword 8-47
min(x,y) function 7-10
minimum
   number size 9-11
   value, measuring 8-46
MINVAL keyword 8-46 , 8-52
mixed
   sources 5-6
mixed mode
   simulation 5-50 , 26-4
    See also D2A, A2D
mixed-signal simulation
    See mixed mode
MJ model parameter 20-28
MJSW model parameter 20-28
mobility
   equations, MOSFETs LEVEL 47 22-12
   parameters
      curve fitting 21-11
      MOSFETs
         LEVEL 2 21-10 - 21-11
         LEVEL 3 21-22
         LEVEL 38 21-167
         LEVEL 5 21-35 - 21-36
         LEVEL 8 21-92 - 21-93
   reduction equations, MOSFETs
      LEVEL 2 21-14
      LEVEL 38 21-174
      LEVEL 5 21-47
   temperature equations, JFETs and MESFETs 17-44
.MODEL
   syntax 6-4 , 18-31
model
   parameters See model parameters diodes
model analysis options 9-16 , 9-16 - 9-18
   BJTs, EXPLI 9-19
   DCAP 9-16
   diodes, EXPLI 9-19
   inductors
      GENK 9-19
      KLIM 9-19
   MODSRH 9-16
   MOSFETs 9-18
   SCALM 9-17
   TNOM 9-17
MODEL keyword 10-15 , 13-39
model names, periods in D-3
model parameters
   A2D 5-50
   ACM 20-9
   .ALTER blocks 3-41
   basic 21-2 - 21-4
   BISECTION 30-7
   BJTs 16-6 - 16-13
      base width modulation 16-9
      beta degradation 16-5
      high current Beta degradation 16-10
      junction capacitance 16-11
      LEVEL 2 16-13
      LEVEL 8, HiCUM 16-95
      low current Beta degradation 16-9
      model name 16-4
      noise 16-13
      parasitics
         capacitance 16-12
         resistance 16-10
      temperature
         effects 16-14 - 16-19
         parameters 16-14
      transistor 16-4
      transit time 16-12
   BV 15-4
   capacitance 14-9
   capacitance distribution 13-24
   D2A 5-50 , 5-51 - 5-52
      CHI 5-51
   DCAP 17-6
   DELVTO 13-9
   diodes 15-6
      junction 15-7 , 15-8
         AREA 15-9
         BV 15-11
         capacitance 15-12
         DC 15-9 - 15-11
         diodes
            model 15-7 , 15-10
         LEVEL 15-7 , 15-10
         model names 15-7
      level 15-4
      noise 15-13
      scaling 15-15
      temperature 15-19 - 15-21
   DTEMP 13-5
   Ebers-Moll 16-5
   Fowler-Nordheim diodes 15-48
   geometry, JFETs and MESFETs 17-7
   .GRAPH statement parameters 8-13
   IKF 16-2
   IKR 16-2
   intrinsic limits 22-109
   JFETs 17-6 , 17-29 , 17-35 , 17-46
      ACM 17-22
      capacitance 17-29
      DC
         LEVEL 1 17-19
         LEVEL 2 17-19 - 17-20
         LEVEL 3 17-21 - 17-22
      gate capacitance 17-17 - 17-18
      gate diode DC 17-15 - 17-16
      noise 17-35
      temperature 17-39 - 17-41
   JFETs and MESFETs 17-14
      DCAP 17-6 , 17-25
      GMIN 17-6
      LEVEL 17-13
      level selector 17-3
      NIF 17-13
      PIF 17-13
       See also model parameters, JFETs or model parameters, MESFETs
   LENGTH 13-22
   LEVEL 13-42
   magnetic cores 14-14 - 14-16
   manufacturing tolerances 13-21
   MESFETs 17-6
      noise 17-35
       See also model parameters, JFETs
   metal and poly capacitors 15-13
   MONO 8-13
   MOSFETs 20-14 , 21-76 , 21-79 , 21-81 , 21-82
      LEVEL 59 22-149
      LEVEL 61 22-176
      LEVEL 62 22-184
   op-amps 26-67 , 26-67 - 26-72
      default values 26-72
   output 8-13
   PHOTO 13-22
   range limit 22-49
   RSH 13-9
   scaling 20-12
   sigma deviations, worst case analysis 13-9
   skew 13-8
   SUBS 16-2
   suppressing printout of 9-8
   TEMP 3-20 , 13-5
   temperature analysis 13-5
   TIC 8-13
   TOM model 17-45 , 17-46
   TOX 13-9
   transmission lines
      geometric
         coax models C-26
         models C-24
         twinlead models C-28
      loss parameters C-16
      measured parameters C-36
      planar models C-14
      precomputed parameters C-30
   TREF 13-4 , 13-5 , 13-6
   U models C-14
      basic ELEV parameters C-36
      common planar parameters C-24
      ELEV = 1 parameters C-28
      geometric
         coax parameters C-26
         twinlead parameters C-15
      measured parameters C-35
   wire models 14-2 , 14-4 - 14-5
      table 14-5
   XPHOTO 13-22
model selection
   automatic D-1 - D-4
   failure to find a model D-3
   program 20-9 , D-3
    See also automatic model selection
   syntax 20-14
.MODEL statement 3-30 , 13-5 , 15-6 , 20-4
   BISECTION syntax 30-7
   BJTs 16-3 , 16-4
   BSIM models 21-111
   capacitance 14-9
   diode junction 15-7
   examples, NMOS model 22-53
   ferromagnetic cores 14-12
   for .GRAPH 8-11
   HSPICE version parameter 3-31
   magnetic core 14-12
   model name 3-30
   MOSFETs 20-14
   op-amp 26-66
   OPT method 30-7
   optimization syntax 13-40
   PASSFAIL syntax 30-7
   U model C-13
   VERSION parameter 21-111
   wire RC 14-2
.MODEL statements and MESFETs 17-13
models
   ACM selector 17-3
   algebraic 11-27
   automatic selection 20-9
   BJTs 3-30
      HiCUM 16-93
      quasi-saturation 16-50
      statement 16-4
   BSIM LEVEL 13 3-31
   BSIM2 LEVEL 39 3-31
   bulk charge effect 20-3
   capacitance 14-9 , 20-7
   capacitors 3-30
      model selector 17-3
   characterization 10-14
   Curtice 17-3
   depletion MOS devices 20-3
   device
      capacitor 14-9
      inductor 14-12
      resistor 14-2
   diode 3-30 , 15-4
      define 15-16
      junction 15-7
      scaling 15-14
      statements 15-4
   Ebers-Moll 16-1 , 16-5
   equations
      LEVEL 61 22-178
      LEVEL 62 22-186
   examples, Jiles-Atherton 14-20
   FAQ A-20
   ferromagnetic cores 14-19
   Gummel-Poon 16-1
   IBIS 19-1
   ion-implanted devices 20-3
   JFETs 3-30
   JFETs and MESFETs
      capacitor 17-5
      DC models 17-1
   Jiles-Atherton core 14-19
   junction
      parameters 15-8
      statement 15-7
   LV18 31-7
   LX7, LX8, LX9 31-7
   magnetic core 3-30 , 14-12
   Monte Carlo
      analysis 13-14
      example 13-26
      parameter distribution 13-18
   MOS compare 21-218
   MOSFETs 3-30
      Berkeley
         BSIM3-SOI 22-114
         junction 22-24
      BSIM 21-101
         equations 21-112
         LEVEL 13 example 21-121
      BSIM2 21-179
         equations 21-186
      BSIM3 22-2
         equations 22-10
         Leff/Weff 22-9
      BSIM3-SOI DD 22-161
      BSIM3-SOI FD 22-147 , 22-149 , 22-157
      BSIM3v3
         MOS 22-19
         NQS 22-23
      BSIM4 22-66 , 22-67
      Cypress 21-162 , 21-169
      Empirical 21-19
         equations 21-22
      EPFL-EKV 22-85
         equations 22-92
         NQS equations 22-106
      Frohman-Bentchkowski, equations 21-77
      HP a-Si TFT 21-207
         equations 21-211
      Hspice junction 22-24
      IDS
         LEVEL 5 21-34
            equations 21-43
            example 21-50
         LEVEL 6
            equations 21-60 , 21-71
            example 21-66 , 21-68
         LEVEL 6 and LEVEL 7 21-52
         LEVEL 7 21-88
         LEVEL 8 21-89
            equations 21-93
      LEVEL 55, updates 22-111
      levels 20-3 , 20-4
      LEVELs 49 and 53, equations 22-52
      modified BSIM LEVEL 28 21-147
         equations 21-155
      MOS 21-33
      Philips MOS9 22-56
      quasi-static equations 22-103
      RPI a-Si TFT 22-175 , 22-176
      RPI Poli-Si 22-184
      RPI Poli-Si TFT 22-182
      Schichman-Hodges 21-2 , 21-7
         equations 21-5 , 21-11
      SOSFET's LEVEL 27 21-136
      UFSOI 22-133
   mutual inductors 3-30
   names 3-30
   National Semiconductor 15-50 , 16-55
   op-amps 3-30
      creating 26-65
   optimization 3-30
   parameters
      DTEMP 31-18
      Fowler-Nordheim 15-48
   passive device 14-1
   plot 3-30
   private 3-40
   protecting 3-40
   quasi-saturation 16-50
   reference temperature 13-5
   resistor equations 14-5
   scaling 20-12
      diode 15-14
   selecting 17-3
   silicon-on-sapphire 20-3
   simulator access 3-35
   SOSFET's 20-3
   specifying 3-51 , 20-14
   SPICE capacitor 17-5
   Statz 17-3
   subcircuit MULTI 3-15
   transient 16-5
   types 3-30
   typical set 13-12 - 13-13
   VBIC bipolar transistor 16-57
   wire
      parameters 14-4
      RC 14-2
modified BSIM LEVEL 28
   equations 21-155
   models 21-147
MONO model parameter 8-13
Monte Carlo
   AC analysis 12-5
   analysis 13-2 , 13-3 , 13-26 - 13-34
      demo files 31-27
      distribution options 13-16 - 13-17
   DC analysis 10-15
   time analysis 11-4
MONTE keyword 11-5 , 12-5 , 13-14
MOS
   diodes 20-9
   inverter circuit 2-7
   model 21-33
   op-amp optimization 13-70
MOS2 model 20-4
MOS3 model 20-4
MOSFETs
   Berkeley
      BSIM3-SOI DD 22-161
   BEX factor 21-127
   bulk transconductance 20-23
   capacitance
      effective length and width 20-97
      equations 20-74 - 20-98
      Meyer model 20-57
      models 20-57
      scaling parameters 20-68
   CAPOP 20-69
      capacitance selector 20-74 - 20-98
   channel length modulation temperature equations 20-111
   charge
      conservation model parameters 20-71
      storage modeling 20-57
   conductance 20-22
   construction 20-17
   control options (list) 20-11
   current
      convention 20-21
      flow 8-25
   diodes
      capacitance
         equations 20-46
         model parameters 20-27
         temperature equations 20-106
      DC
         current equations 20-45
         model parameters 20-27
      effective
         areas 20-32
         drain and source resistance 20-33 , 20-36 , 20-41 , 20-44
         saturation current 20-33 , 20-44
      equation 20-45
      GEO element parameter 20-42
      geometry model parameters 20-30
      model
         parameters 20-27
         select 20-26
      resistance
         model parameters 20-29
         temperature equations 20-111
      suppressing 20-37
   drain diffusion area 4-19
   effective
      length and width 20-97
      output conductance 20-54
   element
      names 4-18
      template listings 8-62
   energy gap temperature equations 20-105
   EPFL-EKV NQS equations 22-106
   equation variables and constants 20-20
   equivalent circuits 20-22
      AC analysis 20-24
      AC noise analysis 20-25
      transient analysis 20-23
   examples
      NMOS model 22-53
      PMOS model 22-55
   gate
      capacitance example 20-64
      capacitance model parameters 20-57 , 20-69
      overlap capacitance model parameters 20-70
   impact ionization equations 20-23 , 20-53
   initial conditions 4-20
   isoplanar
      construction 20-18
      silicon gate 20-17
      width cut 20-19
   level parameter 20-14
   LEVELs 6, 7 UPDATE selector 21-57
   Meyer capacitance model parameters 20-71
   mobility temperature equations 20-111
   model
      RPI a-Si TFT 22-175
   model analysis options 9-18 - 9-19
   model parameters
      A0 22-150
      A1 22-150
      A2 22-150
      AGIDL 22-150
      AGS 22-150
      ALPHA0 22-150
      ASD 22-154
      AT 22-156
      B0 22-150
      B1 22-150
      BGIDL 22-150
      BSIM3-SOI FD 22-149
      BSIM4 22-67
      CAPMOD 22-149
      CDSC 22-150
      CDSCB 22-150
      CDSCD 22-151
      CF 22-154
      CGDL 22-154
      CGDO 22-155
      CGSL 22-155
      CGSO 22-155
      change conservation 20-71
      CIT 22-151
      CJSWG 22-155
      CKAPPA 22-155
      CLC 22-155
      CLE 22-155
      CSDESW 22-155
      CSDMIN 22-155
      CTH0 22-156
      DELTA 22-151
      DLC 22-155
      DROUT 22-151
      DSUB 22-151
      DVT0 22-151
      DVT0W 22-151
      DVT1 22-151
      DVT1W 22-151
      DVT2 22-151
      DVT2W 22-151
      DWB 22-152
      DWC 22-155
      DWG 22-152
      effective width/length 21-9
      ETA0 22-152
      ETAB 22-152
      gate capacitance
         basic 20-69
         Meyer 20-71
         overlap 20-70
      impact ionization 20-53
      ISBJT 22-152
      ISDIF 22-152
      ISREC 22-152
      ISTUN 22-152
      K1 22-152
      K2 22-152
      K3 22-152
      K3B 22-152
      KB1 22-152
      KETA 22-152
      KT1 22-156
      KT2 22-156
      KTIL 22-156
      LEVEL 22-149
      Level 60 22-164
      LINT 22-153
      MJSWG 22-155
      MOBMOD 22-149
      NCH 22-149
      NDIO 22-153
      NFACTOR 22-153
      NGATE 22-149
      NGIDL 22-153
      NLX 22-153
      NOIMOD 22-149
      noise 20-99
      NSS 22-154
      NSUB 22-149
      NTUN 22-153
      PBSWG 22-156
      PCLM 22-153
      PDIBLC1 22-153
      PDIBLC2 22-153
      PRT 22-156
      PRWB 22-153
      PRWG 22-153
      PVAG 22-153
      RBODY 22-153
      RBSH 22-153
      RDSW 22-153
      RSH 22-153
      RTH0 22-156
      SHMOD 22-149
      SII0 22-150
      SII1 22-150
      SII2 22-151
      SIID 22-151
      TBOX 22-149
      temperature 20-102
      threshold voltage 20-50
      TNOM 22-156
      TOX 22-149
      TSI 22-149
      TT 22-156
      U0 22-153
      UA 22-154
      UA1 22-156
      UB 22-154
      UB1 22-156
      UC 22-154
      UC1 22-157
      UTE 22-157
      VBSA 22-154
      VERSION 22-20
      VOFF 22-154
      VSAT 22-154
      VSDFB 22-156
      VSDTH 22-156
      VTH0 22-154
      WINT 22-154
      WR 22-154
      XBJT 22-157
      XDIF 22-157
      XPART 22-156
      XREC 22-157
      XTUN 22-157
       See also Chapter 20
   models
      AMD 20-5 , 20-6
      AMI-ASPEC 20-5
      ASPEC-AMI 20-5
      Berkeley
         BSIM3-SOI 20-7 , 22-114
         BSIM3-SOI DD 22-161
         junction 22-24
      BSIM 20-5 , 21-101
         equations 21-112
         LEVEL 13 example 21-121
      BSIM2 20-6 , 21-179
         equations 21-186
      BSIM3 20-6 , 22-2
         equations 22-10
         Leff/Weff 22-9
      BSIM3-SOI FD 22-147
      BSIM3v3
         MOS 22-19
         NQS 22-23
      BSIM4 22-66
      CASMOS 20-5
         GEC 20-5
         model (GTE style) 20-5
         Rutherford 20-6
      Cypress 20-5 , 21-162 , 21-169
      Dallas Semiconductor 20-5
      Empirical 21-19
         equations 21-22
      EPFL-EKV 20-7 , 22-85
         equations 22-92
      Fluke-Mosaid 20-5
      Frohman-Bentchkowski, equations 21-77
      GE-CRD-Franz 20-5
      GE-Intersil 20-6
      Grove-Frohman 20-4
      HP a-Si TFT 21-207
         equations 21-211
      Hspice junction 22-24
      HSPICE PC version 20-4
      IDS
         Cypress depletion 20-6
         LEVEL 5 21-34
            equations 21-43
            example 21-50
         LEVEL 6
            equations 21-60 , 21-71
            example 21-66 , 21-68
         LEVEL 7 21-88
         LEVEL 8 21-89
            equations 21-93
      Lattin-Jenkins-Grove 20-5
      LEVEL 61 circuit 22-178
      LEVEL 62 22-186
      levels 20-4
      LEVELs 49 and 53 equations 22-52
      modified BSIM LEVEL 28 21-147
         equations 21-155
      MOS 21-33
         compare 21-218
      MOS2 20-4
      MOS3 20-4
      MOS9 22-56
      Motorola 20-6
      National Semiconductor 20-6
      Philips MOS9 22-56
      quasi-static, equations 22-103
      RPI a-Si TFT 22-176
      RPI Poli-Si parameters 22-184
      RPI Poli-Si TFT 22-182
      Schichman-Hodges 20-4 , 21-2 , 21-7
         equations 21-5 , 21-11
      SGS-Thomson 20-6
      Sharp 20-6
      Siemens 20-5 , 20-6
      Sierra 1 20-5
      Sierra 2 20-6
      Siliconix 20-5
      SOSFET's 20-6
         LEVEL 27 21-136
      statement 20-14
      STC-ITT 20-5
      Taylor-Huang 20-5
      TI 20-6
      University of Florida SOI 20-7 , 22-133
      user defined 20-5
      VTI 20-6
   n-channel specification 20-14
   node names 4-18
   noise 20-99
      model equations 20-99
      model parameters 20-99
      summary printout 20-101
   p-channel specification 20-14
   perimeter
      drain junction 4-19
      source junction 4-19
   power dissipation 8-28
   saturation current temperature equations 20-106
   SCALM 9-18
   sensitivity factors 21-154
   source
      diffusion area 4-19
      drain sharing selector 4-20
   SPICE compatibility 20-4
   squares
      per drain diffusion 4-19
      per source diffusion 4-19
   surface potential temperature equations 20-109
   temperature
      coefficient model parameters 20-104
      differential 4-20
      effects parameters 20-102
      parameters 20-102
   template input
      BSIM3-SOI FD 22-157
   threshold voltage
      model parameters 20-50
      temperature equations 20-110
   transconductance 20-22
   UPDATE parameter usage 21-128
   WIC ids current selector 21-73
   WL 9-18
   zero-bias voltage threshold shift 4-20
Motorola model 20-6
MS model parameter 14-19
.ms# file 3-55 , 3-56
MSPICE simulator interface 9-12
.mt# file 3-55 , 3-56
MU option 9-49 , 11-17
Muller algorithm 27-3
   starting points 9-37 , 10-33
MULTI 3-15
multiconductor capacitance/conductance C-32
multiconductor systems 18-3
Multi-Level Gamma model, example 21-66 , 21-68
multiple .ALTER statements 3-42
multiplier
   function, U and T Elements C-5
   G and E Element values 29-11
   GSCAL 9-36 , 10-32
multiply parameter 3-48 , 4-3 , 5-3
   subcircuits 3-15
multipoint experiment 1-8
   examples 1-8
multi-terminal network 6-1
multithreading 3-63
mutual
   inductance C-76
   inductor
      coupling coefficient 14-18
      element 4-9
         template listings 8-56

N

N model parameter 20-27
NAND gate adder 31-4
narrow width effect 21-13
National Semiconductor model 16-55 , 20-6
   converting 15-50
natural
   frequency 27-2
   log function 7-10
NB model parameter 15-36 , 20-28
n-channel, MOSFET's models 3-30
ND model parameter C-14
NDIM 5-24
NDS model parameter 20-27
negative conductance, logging 9-15
nested library calls 3-33
.NET statement 12-14
netlist 3-6
   AvanLink B-6
   AvanLink-DA B-12
   encrypting E-1
   FAQ A-27
   flat 3-6
   input files 3-2
   schematic 3-6
network
   analysis 12-14
   filenames 3-29
   multi-terminal 6-1
   output 8-34 , 12-15
   switched capacitor 29-48
   variable specification 12-18
NEWTOL option 9-34 , 10-26
NG model parameter 15-36
NL model parameter C-24
NLAY model parameter C-16 , C-24
nodal voltage output 8-21 , 8-30
NODE option 9-7
   suppressing listing 3-40
nodes
   connection requirements 3-17
   cross-reference table 9-7
   floating supply 3-17
   global versus local 3-20
   internal 3-18
   MOSFET's substrate 3-17
   names 3-16 , 3-17 , 3-19 , 31-7
      automatic generation 3-19
      ground node 3-17
      period in 3-17
      subcircuits 3-17 , 3-18
      zeros in 3-19
   numbers 3-16 , 3-17
   phase or magnitude difference 8-31
   printing 9-7
   shorted 10-47
   terminators 3-17
   voltages, encrypting E-1
NODESET keyword 10-12
.NODESET statement 9-29 , 10-3 , 10-23 , 27-3
   balancing input nodes 26-66
   DC operating point initialization 10-10
   from .SAVE 10-12
node-to-element list 9-25 , 9-27 , 10-28 , 10-31
NOELCK option 9-8
Noise 22-43
noise
   analysis 16-58
   BJTs 16-6
   calculations 12-12
   CMI_Noise 23-29
   coupled line
      example 25-27
      noise 25-27
   equations
      BJTs 16-40
      JFETs and MESFETs 17-35
      junction diode 15-28
      resistor 14-7
   folding 12-13
   input 8-35
   JFETs and MESFETs
      equations 17-35
      summary printout 17-37
   MOSFETs 20-99
      equivalent circuits 20-25
      models
         EPFL-EKV equations 22-107
   numerical 9-39 , 11-12
   output 8-35 , 12-12
   parameters 15-13 , 16-13
      BJTs 16-13
      JFETs and MESFETs 17-35
      MOSFETs
         BSIM3v3 22-43
         LEVEL 55 22-91
   problems and solutions 25-3
   quota 25-6 , 25-8
   resistor 14-7
      equation 14-7
   sampling 12-13
   sources 25-3 , 25-5
   thermal 14-7
.NOISE statement 12-11
NOISENPT
   frequency Table Model 6-4
NOMOD option 9-8
NONE keyword 10-7 , 10-13
nonlinear elements 29-2
NonQuasi-Static (NQS) model 22-23
   equations 22-106
   parameters 22-45
nonvolatile memory diodes 15-1
NOPAGE option 9-8
NOPIV option 9-23 , 10-26
NORM FFT analysis keyword 28-7
norm of the gradient 13-53
Normal Field equations 21-78
NOTOP option 9-8
NOWARN option 9-15
NP .FFT parameter 28-7
NPDELAY element parameter 26-13 , 26-19 , 26-24 , 26-29
npn BJT models 3-30
NPWL
   element parameter 26-19
   function 5-35 , 26-17
   NMOS transistor function 26-10
NS model parameter 15-36
NSUB model parameter 20-28
NT, FAQ A-23
numbers
   formatting 9-6 , 9-7
   maximum size 9-11
   minimum size 9-11
NUMDGT option 9-8
numerical
   integration
      algorithms 9-49 , 11-14
      order of 9-48 , 11-14
   noise 9-39 , 11-12
      problems 9-34 , 9-39 , 10-25 , 11-12
NUMF keyword 12-13
NXX option 9-6 , 9-8
Nyquist critical frequency 29-5 , 29-11

O

obtaining customer support vi
O.C.G. matrix C-33
OCT keyword 10-16 , 11-6 , 12-6
OD1 model parameter C-29
odelay (digital vector file) 5-73
OFF
   element parameter 9-35 , 10-4 , 10-27
   option 9-35 , 10-4 , 10-27
one-dimensional function 5-25
ON/OFF Condition 15-41
ONOISE parameter 8-35
.OP statement 10-5 , 10-6 , 11-3
.OP statement parameters 10-6
OPAMP element parameter 26-13
op-amps
   automatic generation 26-5
   behavioral models 26-65
   characterization 24-7
   common mode rejection ratio 26-68
   compensation level selector 26-68
   diode and BJT saturation current 26-69
   element statement 26-66
   excess phase parameter 26-69
   gain parameter 26-67
   input
      bias current 26-69
      bias offset current 26-70
      level type selector 26-70
      offset current 26-70
      offset voltage 26-72
      short circuit current 26-70
   internal feedback compensation capacitance 26-68
   JFETs saturation current 26-70
   mA741 model 26-76
   manufacturer's name 26-70
   model
      generator 26-65
      names 3-30
      parameters 26-67
         defaults 26-72
      selector 26-68
   .MODEL statement 26-66
   open loops 10-46
   optimization 13-70
   output
      level type selector 26-70
      resistance ROAC 26-71
      slew rate 26-71
      voltage 26-72
   phase margin 26-69
   power
      dissipation 26-70
      supply voltage 26-71
   subcircuit example 26-74
   subcircuit generator 26-5
   temperature parameter 26-71
   unity gain frequency 26-69
operating point
   capacitance
      printout 20-61
      values table 9-28 , 10-22
   Early voltage 22-108
   estimate 10-5 , 11-3
   .IC statement initialization 10-9
   initial conditions 3-54
   .NODESET statement initialization 10-10
   numerical values of model internal variables 22-108
   Overdrive voltage 22-108
   pole/zero analysis 27-3
   restoring 10-13
   saturation / non-saturation flag 22-109
   saturation voltage 22-108
   saving 3-19 , 10-12
   solution 9-35 , 10-3 , 10-4 , 10-27
   SPICE-like threshold voltage 22-108
   transconductance efficiency factor 22-108
   transient 11-3
   voltage table 10-7
operating systems, HSPICE 1-6
operators
   arithmetic 7-9
   Laplace transforms 29-22
OPT keyword 13-38 , 30-8
optimization
   AC analysis 12-4 , 13-60
   algorithm 13-42
   analysis statements 13-39
   behavioral models 26-46 , 26-50
   bisection method 30-5 , 30-7
   CMOS tristate buffer 13-55
   control 13-36
   convergence options 13-36
   curve-fit 13-37
   cv 31-33
   data-driven vs. s-parameters 13-61
   DC analysis 10-15 , 13-46 , 13-48 , 13-63 , 13-67
   error function 8-40
   example 13-44 , 31-24
   goal 13-37
   incremental 13-63
   iterations 13-42
   lengths and widths 13-70
   MODEL keyword 13-39
   .MODEL statement 13-40
   models 3-30
   MOS
      LEVEL 13 13-48
      op-amp 13-70
   network 13-60
      RC 13-51
   .PARAM statement 13-39
   parameters 13-60
      magnitude and phase 13-61
      measured vs. calculated 13-61
      .MODEL statement 13-41 - 13-43
   results
      function evaluations 13-53
      iterations 13-54
      Marquadt scaling parameter 13-53
      norm of the gradient 13-53
      residual sum of squares 13-52
   S parameters 13-60
   simulation accuracy 13-36
   simultaneous 13-56 , 13-67 , 13-70
   statements 13-38
   syntax 13-38
   TDR
      packaging 25-9
      procedure 25-11
   time
      analysis 11-5 , 13-37
      required 13-36 , 13-41
OPTIMIZE
   function 26-3
   keyword 10-15 , 13-38
.OPTION 10-29 , 10-31
   ACCT, summary of job statistics 8-16
   ALT999 or ALT9999, for output file name extension 8-14
   AUTOSTOP 26-74
   CO, for printout width 8-14
   DCAP 15-5 , 16-2 , 16-3
   DCCAP 15-5
   DCSTEP 10-47
   DI 9-21 , 9-39 , 10-39 , 11-16 , 12-8
   GMIN 15-5 , 16-2
   GMINDC 15-5 , 16-2
   GRAMP 16-2
   INGOLD, for printout numerical format 8-15
   keyword application table 9-3
   MBYPAS 20-13
   POST, for high resolution graphics 8-15
   RISETIME 18-12 , 18-13
   SCALE 15-4 , 15-14
   SCALM 15-4 , 15-14
   SHRINK 15-14
   statement 9-2 , 10-31
      .ALTER blocks 3-41
options
   control, setting 15-4
   convergence 15-5
   EPSMIN 29-20
   FAQ A-27
   OPTLST 30-8
.OPTIONS SEARCH statement 3-36
OPTLST option 9-8 , 30-8
   printing bisection results 30-8
OPTS option 9-9
OPTxxx parameter 13-37 , 13-38
Opus 9-11
oscillation
   eliminating 9-49 , 11-14
   from simulation errors C-61
oscillators
   behavioral models 26-65
   DELMAX option setting 11-26
   LC 26-83
   VCO 26-81
out (digital vector file) 5-76
outer sweep 3-25
output
   admittance 8-34
   buffer 19-8 , 19-9
      example 19-42
   commands 8-2
   conductance 20-54
   current 8-22
   data
      format 9-6 , 9-7 , 9-12
      limiting 9-12 , 9-50 , 11-12
      number format 9-6
      redirecting 3-61
      significant digits specification 9-8
      specifying 9-12 , 9-13
      storing 9-12
   driver example 31-12
   ECL buffer 19-20
   FAQ A-32
   .FFT results 28-10
   files 3-55
      names 3-53 , 3-61
      redirecting 3-53
      reducing size of 9-12 , 9-15
      version number, specifying 3-60
   graphing 8-10
   impedance 8-34
   magnetic core 14-16
      LX1 - LX7 14-16
   measfail value 30-8
   .MEASURE results 8-37
   network 8-34
   nodal voltage, AC 8-30
   noise 8-35 , 12-12
   parameters 8-21
   plotting 8-8 - 8-9
      specifying variables 8-10
   power 8-25
   printing 8-6 - 8-20
   printout format 8-15
   saving 8-9
   statements 8-2
   variables 8-3
      AC formats 8-32
      function 7-11
      printing 9-50 , 11-13
      probing 8-10
      specifying significant digits for 9-8
   voltage 8-21
outz (digital vector file) 5-76
overlap capacitors 20-73
overlay dielectric transmission line C-21
overview
   data flow 1-9
   simulation process 1-10

P

.pa# file 3-55 , 3-57
packed input files 3-2
Pade approximation 29-40
page eject, suppressing 9-8
PAR
   keyword 7-4 , 7-8
   parameter, example 24-11
.PARAM statement 3-15 - 3-20 , 3-37 , 8-38 , 13-2
   in .ALTER blocks 3-41
   optimization 13-39
parameters
   AC sweep 12-4
   ACM 11-27
   admittance (Y) 8-29
   AF 12-13
   algebraic 7-9
      expressions 7-8
   analysis 7-6
   AREA 15-6
   assignment 7-3
   base width 16-9
   BJT LEVEL 2 16-13
   capacitance 14-9
   capacitor
      junction 16-11
      metal and poly 15-13
   CAPOP 11-27
   cell geometry 7-13
   constants 7-3
   data
      driven analysis 3-21
      type 7-2
   DC
      model 16-5
      sweep 10-14
   defaults 7-17
   defining 7-2 , 7-14
   DIM2 8-35
   DIM3 8-35
   Ebers-Moll 16-5
   encrypting E-1
   evaluation order 7-3
   extraction example 14-24
   .FFT statement 28-7 - 28-8
   frequency response table 29-9
   HD2 8-35
   HD3 8-35
   hierarchical 3-48 , 7-13 , 8-38 - 8-39
   high-current beta degradation 16-10
   hybrid (H) 8-29
   IC 10-9
   impedance (Z) 8-29
   inheritance 7-16 , 7-17
   INOISE 8-35
   input netlist file 3-5
   junction
      capacitor 16-5
      diode 15-6
      setting
         capacitance 15-12
         DC LEVEL 1 and 3 15-9
   KF 12-13
   Laplace 29-9
   libraries 7-14 - 7-17
   limit checking
      capacitor device 14-10
      magnetic core 14-17
   low-current beta degradation 16-9
   M 3-48 , 7-7
   matrix 12-14
   measurement 7-7
   model
      A2D 5-54
      BJT LEVEL 2 16-13
      D2A 5-51
      Fowler-Norheim 15-48
      Jiles-Atherton core 14-16
      Juncap 15-35
      junction 15-8
      magnetic core 14-14
      wire 14-4
   modifying 3-21
   multiply 7-7
   names 3-31
   noise 15-13 , 20-99
      BJTs 16-13
      JFETs and MESFETs 17-35
   ONOISE 8-35
   optimization 7-13
   OPTxxx 13-37 , 13-38
   output 8-21
   overriding
      assignments 7-15
      default values 7-5
   PAR keyword 7-4
   PARHIER option 7-17
   passing 7-13 - 7-19
      example 24-11
      order 7-3
      problems 7-19
      Release 95.1 and earlier 7-19
   pole/zero 29-9
   repeated 8-38
   resistance 16-10
   scattering (S) 8-29
   scope 7-13 - 7-14 , 7-19
   SIM2 8-35
   simple 7-3
   simulator access 3-35
   skew, assigning 3-35
   subcircuit 3-48 , 7-5
   temperature, JFETs and MESFETs 17-38
   time sweep 11-4
   transient model 16-5
   transit time 16-5 , 16-12
   transmission lines 18-3 , 18-34
   UIC 10-10
   user-defined 7-4
   UTRA 10-45
   varying example 14-20
   VBIC 16-57
   voltage 20-50
    See also model parameters, optimization parameters
parametric analysis 8-4
parasitic
   capacitance 16-12
      BJTs 16-6
         parameters 16-12
      RC wire model 14-2
   diode, MOSFETs LEVEL 39 21-198
   generation 20-37
   MOSFETs LEVEL 13 21-126
   resistance
      parameters, BJTs 16-10
      temperature equations
         BJTs 16-49
         JFETs and MESFETs 17-44
PARHIER option 7-17
PARMIN optimization parameter 13-43
PASSFAIL keyword 30-8
passive device models 14-1
path names 9-9
   subcircuits 3-18
path numbers, printing 9-9
PATHNUM option 9-9
PB model parameter 15-36 , 20-28
PC, FAQ A-23
p-channel
   JFETs models 3-30
   MOSFET's models 3-30
PCI 31-36
   demo files 25-37
   driver selection 25-42
   Hspice file 25-37
   modeling 25-33
   simulation
      example files 25-46
      process 25-45
   Speedway 25-35
      circuit schematic 25-43
      models D-15
      subsections 25-43
PD model parameter 26-70
peak-to-peak value, measuring 8-46
period (digital vector file) 5-71
peripheral component interconnect
    See PCI
permit.hsp file, encryption capability E-7
PG model parameter 15-37
PHA model parameter 20-28
phase
   AC voltage 8-31 - 8-32
   calculating 8-31
   detector model 26-88 , 26-97
   locked loop, BJT model 26-92
PHD model parameter 20-28
Philips MOS9 model 22-56
PHOTO model parameter 13-22
PHP model parameter 20-28
PHS model parameter 20-28
piecewise linear sources See PWL
pin capacitance, plotting 24-6
pivot
   algorithm, selecting 9-24 , 9-26 , 10-27
   change message 9-25 , 9-27 , 10-28 , 10-31
   matrix calculations 9-23 , 10-26
   reference 9-25 , 10-28
   selection 11-24
PIVOT option 9-24 , 9-26 , 10-27 , 11-24
PIVREF option 9-25 , 10-28
PIVREL option 9-25 , 10-29
PIVTOL option 9-24 , 9-25 , 9-26 , 10-28 , 10-29 , 10-30
PJ capacitor, parameter 15-6
planar conductor parameters C-20
platforms for Hspice 1-6
PLEV model parameter C-7 , C-13 , C-14 , C-36
PLIM option 9-9
PLL See phase locked loop
plot
   limits 8-8
   models 3-30
   value calculation method 9-5 , 9-39 , 12-7
PLOT keyword 8-12
.PLOT statement 8-2
   in .ALTER block 3-40
   simulation results 8-8 , 8-19
PMOS model
   examples 22-55
pn junction conductance 10-54
pnp BJT models 3-30
POI keyword 10-16 , 11-6 , 12-6
POLE
   element parameter 29-11
   function 27-1 , 29-2 , 29-7 , 29-28 - 29-33
      call 29-28
      highpass filter 29-31
      low-pass filter 29-32
      transconductance element statement 29-7
      voltage gain element statement 29-7
poles and zeros, complex 29-30
pole/zero
   analysis 27-1 , 29-2
      absolute tolerance 9-36 , 10-32 , 27-4
      capacitance scale 27-4
      conductance scale 27-4
      example
         active low-pass filter 27-15
         CMOS differential amplifier 27-12
         high-pass Butterworth filter 27-10
         Kerwin's circuit 27-8
         low-pass filter 27-5
         simple amplifier 27-14
      frequency
         maximum 9-35 , 10-31
         scale 27-4
      imaginary to real ratio 27-5
      inductance scale 27-4
      iteration limit 27-4
      maximum
         frequency 27-4
         number of iterations 9-42 , 10-31
      Muller algorithm 27-3
      operating point 27-3
      overview 27-2
      .PZ statement 27-3
      real to imaginary ratio 9-36 , 10-32 , 27-5
      relative error tolerance 27-5
      starting points, Muller algorithm 9-37 , 10-33
   conjugate pairs 29-8
   control options 9-35 - 9-37 , 27-4 , 27-4 - 27-5
   function, Laplace transform 29-7
   models 29-43
      AC analysis 29-47
      transient responses 29-46
   parameters 29-9
   transfer function 29-28
   transient modeling 29-2
POLY 5-24
   element parameter 26-7 , 26-13 , 26-20 , 26-25 , 26-29
polygon, defining 18-40
polynomial function 5-24 , 26-7
   FV function value 26-7
   one-dimensional 5-25
   three-dimensional 5-27
   two-dimensional 5-26
polysilicon 20-17
POST option 1-9 , 9-12
POST_VERSION option 9-9
pow(x,y) function 7-9
power
   dissipation 8-25 - 8-29
      subcircuits 8-25
   function 7-10
   operating point table 10-6
   output 8-25
   stored 8-25
POWER keyword 8-26
PP keyword 8-46 , 8-47
PPWL
   element parameter 26-20
   function 5-36 , 26-17
   PMOS transistor function 26-10
PRD model parameter 20-29
precision numbers 7-8
print
   CMI_PrintModel 23-31
   control options 8-14
.PRINT statement 8-2
   in .ALTER 3-40
   simulation results 8-5 , 8-19
printed circuit boards
   models 25-2
printer, device specification 8-10
printout
   columns, number 9-6
   disabling 9-6 , 9-8
   suppressing 3-40
      page ejects 9-8
   value calculation method 9-5 , 9-39 , 12-7
PROBE option 9-12
.PROBE statement 8-2
   simulation results 8-9 , 8-19
program structure 1-7
.PROTECT statement 3-40 , E-2
protecting data 3-40
PRS model parameter 20-29
PRTDEFAULT printer 8-10
PS model parameter 15-37
PSF option 9-12
PSRR specification 26-5
PULSE source function 5-7 , 5-10 , 5-13 , 5-15
   delay time 5-8
   initial value 5-8
   onset ramp duration 5-8
   plateau value 5-8
   recovery ramp duration 5-8
   repetition period 5-8
   width 5-8
pulse width 30-16
PUTMEAS option 8-38 , 9-51
PWL
   current controlled gates 26-6 , 26-7
   data driven 5-18
   element parameter 26-13 , 26-20 , 26-25 , 26-29
   functions 5-28 , 26-7 , 26-10
   gates 26-6
   NMOS and PMOS transistor functions 26-10
   output values 5-16
   parameters 5-15
   repeat parameter 5-16
   segment time values 5-16
   simulation time 11-36
   sources, data driven 5-18
   voltage controlled
      capacitors 26-6
      gates 26-6
    See also data driven PWL source
PWR model parameter 26-70
pwr(x,y) function 7-10
.PZ statement 10-19 , 27-3 , 29-2
PZABS option 9-36 , 10-32 , 27-4
PZTOL option 9-36 , 10-32 , 27-5

Q

quality assurance 13-2
quasi-saturation BJT model 16-50
quasi-static model equations 22-103

R

RA model parameter C-26
RA1 model parameter C-28
RAC model parameter 26-71
radix (digital vector file) 5-68
random limit parameter distribution 13-14
RB model parameter C-26
RC
   line modeling 29-33
   network
      analysis
         AC 2-2
         transient 2-5
      circuit 2-2
      optimization 13-51
   wire model 14-2
rcells, reusing 7-14
RD model parameter 20-29 , C-26
RDC model parameter 20-29
real part of AC voltage 8-31
real vs. imaginary component ratio 9-36 , 10-32
RECT FFT analysis keyword 28-8
rectangle, defining 18-38
rectangular FFT window 28-4
reference
   IBIS 19-49
   plane, transmission lines C-5
   temperature 3-20 , 13-5
regions charge equations, MOSFETs LEVEL 13 21-118
related documents iii
RELH option 9-22 , 9-40 , 10-40 , 11-18 , 12-8
RELI option 9-22 , 9-40 , 10-35 , 10-41 , 11-18
   KCLTEST setting 9-21 , 10-26
RELIN optimization parameter 13-43
RELMOS option 9-20 , 9-22 , 10-35 , 10-37 , 10-41 , 11-27
   KCLTEST setting 9-21 , 10-26
RELOUT optimization parameter 13-43
RELQ option 9-40 , 11-18 , 11-34
RELTOL option 9-39 , 9-40 , 11-16 , 11-18
RELV option 9-22 , 9-40 , 9-42 , 10-35 , 10-41 , 11-17 , 11-18
   multiplier for 9-43 , 11-17
RELVAR option 9-46 , 11-18 , 11-27
RELVDC option 9-22 , 9-23 , 10-41
repeat function 31-3
residual sum of squares 13-52
resistance
   AC 12-3
   matrices 18-4
   minimum 9-35 , 10-29
   MOSFETs model parameters 20-29
   parameters 16-10
resistor
   BJTs 16-6
   current flow 8-23
   device model 14-2
   element 4-2
   element template listings 8-55
   length parameter 4-3
   model
      equations 14-5
      name 4-2
   node to bulk capacitance 4-3
   noise 14-7
      equation 14-7
   temperature 14-8
      equations 14-8
   voltage controlled 5-35
   width parameter 4-3
   wire model parameters 14-5
RESMIN option 9-35 , 10-29
RESULTS keyword 10-15
RHO model parameter C-16 , C-25 , C-26 , C-28
RHOB model parameter C-16 , C-25 , C-26 , C-29
RIN keyword 12-15
ripple calculation 24-3
rise and fall times 8-39
RISE keyword 8-41
rise time C-79
   simulation example 24-2 , 24-9
RISETIME option 9-40 , 18-12 , 18-13
RITOL option 9-36 , 10-32 , 27-5
RL model parameter 20-29
RLGC
   element syntax 18-27
   model syntax 18-28
RLOAD model parameter 5-54
RMAX option 9-46 , 11-23 , 11-35
RMIN option 9-46 , 11-23 , 11-35
RMS keyword 8-47
rms value, measuring 8-46
roac model parameter 26-71
ROUT keyword 12-15
ROUT model parameter 26-71
row/matrix ratio 9-25 , 10-29
RPI
   a-Si TFT model 22-175
      circuit 22-178
      parameters 22-176
   Poli-Si model
      parameters 22-184
   Poli-Si TFT model 22-182
      circuit 22-186
RS model parameter 20-29
RSC model parameter 20-29
RSH model parameter 13-9 , 20-29
runtime statistics 9-5

S

S Element 6-2
   Frequency Table Model 6-4
   syntax 6-3
   transmission line 6-8
S parameter
   example 6-8
   model type 3-30
   S Element 6-2
   transmission line 6-10
S19NAME model parameter 5-55
S19VHI model parameter 5-55
S19VLO model parameter 5-55
S1NAME model parameter 5-54
S1VHI model parameter 5-55
S1VLO model parameter 5-55
.SAMPLE statement 12-13
sampling noise 12-13
saturable core
   elements 8-65
      names 4-10
      winding names 4-10
   models 14-12
      names 4-10
   winding names 8-65
saturation
   carrier velocity 21-83
   current temperature equations
      JFETs and MESFETs 17-41
      MOSFETs 20-106
   temperature equations, BJTs 16-42
   voltage (vdsat), BSIM LEVEL 13 21-115
   voltage equations, MOSFETs
      LEVEL 1 21-6
      LEVEL 13 21-115
      LEVEL 2 21-14
      LEVEL 28 21-158
      LEVEL 3 21-25
      LEVEL 38 21-173
      LEVEL 47 22-12
      LEVEL 5 21-47
      LEVEL 6 21-65 , 21-70
      LEVEL 8 21-95
.SAVE statement 10-11
.SAVE statement parameter 10-13
SCALE 15-4
   element parameter 26-13 , 26-20 , 26-25 , 26-29 , 29-11
   option 14-5 , 14-10 , 15-4 , 15-14 , 31-7
   parameter 29-37
scale
   diode parameters 15-15
   factor 4-3
   JFETs and MESFETs 17-6
      parameters 17-7
SCALE option 20-11 , 20-12
scaling 20-12
   BJTs 16-20
   diode model 15-14
   effect on delays 31-23
   global SCALM override 20-12
   global vs model 15-4 , 20-12
   JFETs 17-6
   MOSFETs capacitance parameters 20-68
   options 15-4
SCALM 15-4
   option 9-18 , 14-5 , 14-10 , 15-4 , 15-14 , 20-11
      JFETs and MESFETs scaling 17-6
   parameter
      global scaling 20-12
      in a diode model statement 15-4
      overriding in a model 20-12
      scaling by model 20-12
scattering (S) parameters 8-29
    See also S parameter 6-2
schematic
   AvanLink B-5
   AvanLink-DA B-10
   netlists 3-6
Schichman-Hodges model 20-4 , 21-2 , 21-7
   equations 21-11
Schmitt trigger example 10-18
Schottky barrier diodes 15-1
scope of parameters 7-14
scratch files 1-12
SDA option 9-12
s-domain 29-20
   equivalent circuit 29-25
SEARCH option 3-36 , 3-52 , 9-9 , 31-20
search path, setting 3-37
SEED option 9-15
self inductance C-77
.SENS statement 10-19
sensitivity
   analysis 10-19
   factors, MOSFETs LEVEL 28 21-154
setup time 30-4
   analysis 30-6 , 30-10
SFFM source function
   carrier frequency 5-20
   modulation index 5-20
   output amplitude 5-20
   output offset 5-20
   signal frequency 5-20
sgn(x) function 7-10
SGS-Thomson MOS model 20-6
shape
   circle 18-39
   defining 18-38
   polygon 18-41
   rectangle 18-38
   strips 18-40
Sharp model 20-6
short-channel effect 21-13
shorted nodes 10-47
SHRINK
   model parameter 14-5 , 14-10
   option 15-14
SHTHK model parameter C-26 , C-29
Siemens model 20-5 , 20-6
Sierra 1 model 20-5
Sierra 2 model 20-6
SIG
   conductivity C-89
   model parameter C-16 , C-25 , C-26 , C-28
SIG1 model parameter C-25
sigma model parameter, sweeping 24-4
sign
   function 7-10
   transfer function 7-10
   (x,y) function 7-10
signal integrity
   problems 25-3
SIGNAME element parameter 5-54
signed power function 7-10
Signetics
   device models D-15
   FAST I/O drivers 25-18
silicon
   controlled rectifier, behavioral 26-59
   gate transistor 20-17
Siliconix model 20-5
silicon-on-sapphire devices 20-3
   bulk node name 3-19
SIM2 21-179
   distortion measure 12-9
   parameter 8-35
Simpson Integration 20-86
simulation
   accuracy 9-38 , 9-48 , 11-13 , 11-16 , 11-25 , 13-36 , 21-4
      improvement 9-44 , 11-12
      models 11-27
      option 11-28
         defaults 11-35
      reduced by BYPASS 9-42 , 11-11
      timestep 11-26
      tolerances 10-34 , 10-35
   AvanLink B-7
   AvanLink-DA B-12
   circuits
      with Signetics drivers 25-18
      with Xilinx FPGAs 25-22
   electrical measurements 31-20
   example F-1
   graphical output F-10
   ground bounce example 25-24
   interconnect C-10
   multiple analyses, .ALTER statement 3-40
   multiple runs 3-45
   PCI 25-45
      example 25-46
   performance, multithreading 3-63
   preparation 25-2
   process, overview 1-10
   results
      graphing 8-10
      output variables 9-12
      plotting 8-8 - 8-9
      printing 8-6 - 8-20
      specifying 8-37 - 8-39
      storing 9-12
   speed 9-8 , 11-25
   structure 1-7
   time 21-4
      ABSVAR option 11-35
      reducing 3-22 , 9-41 , 9-42 , 9-44 , 9-45 , 9-47 , 9-48 , 11-11 , 11-12 , 11-17 , 11-19 , 11-20 , 11-22 , 11-36 , 29-48
         with TRTOL 9-41 , 11-19
      RELVAR option 11-35
   title 3-9
SIN source function 5-11
sin(x) function 7-9
single point experiment 1-8
single-frequency FM source function 5-20
sinh(x) function 7-9
sinusoidal source function 5-10
skew
   file 13-12
   parameters 13-8
      assigning 3-35
Skin 18-13
skin effect
   imaginary term handling 18-13
skin effect frequency C-18
slope (digital vector file) 5-74
SLOPETOL option 9-47 , 11-19
   simulation time 11-36
   timestep control 11-35
small-signal
   DC sensitivity 10-19
   distortion analysis 12-9
   transfer function 10-20
SMOOTH element parameter 26-20
SOI model 21-142
SONAME model parameter 5-54
SOSFET's model 20-3 , 20-6
   LEVEL 27 21-136
source
   AC sweep 12-4
   controlled 26-4 , 26-6
   data driven 5-18
   DC sweep 10-14
   element types 26-6
   keywords 5-2
   Laplace transforms 29-21
   statements 3-10
   time sweep 11-4
    See also independent sources
SOVHI model parameter 5-54
SOVLO model parameter 5-54
.sp file encryption E-10
SP model parameter C-15 , C-24
SP12 model parameter C-24
SPARSE option 9-26 , 10-30
spatial extent of leading edge C-83
spectral leakage 28-3 , 28-16
spectrum analysis 28-1
SPICE
   compatibility 9-14 , 17-22
      AC
         output calculations 9-5 , 9-39 , 12-7
         output variables 8-30 - 8-32
      BSIM model 21-123
      diodes 20-37
      models 21-218
      MOSFETs
         LEVEL 13 parameters 21-123
         LEVEL 3 21-29
         LEVEL 39 21-182 , 21-191
         models 20-4
      numeric format 9-6
      plot
         limits 8-8
         size 9-9
      UTRA model parameter 21-11
   depletion capacitor model 17-5
   Meyer gate capacitances 20-74
   model parameters, MOSFETs LEVEL 39 21-182
   option 9-14
sqrt(x) function 7-9
square root function 7-9
SRN model parameter 26-71
SRNEG model parameter 26-71
SRP model parameter 26-71
SRPOS model parameter 26-71
.st# file 3-55 , 3-57
stacked devices 20-41
Star-Hspice Δ L equation 21-85
START .FFT parameter 28-7
START keyword 11-6
statements
   .AC 12-4 , 13-5 , 13-39
   .ALTER 3-40
   call
      subcircuit 3-14
   .DATA 3-21 , 24-9
      external file 3-25 , 3-27
      inline 3-23
      inner sweep example 3-24
      outer sweep example 3-25
   .DC 10-14 , 13-5 , 13-39
   .DCVOLT 10-9 , 10-10
   .DEL LIB 3-42
   .DISTO 12-9
   element 3-10
   .END 3-45
   .ENDL 3-32 , 3-33
   .ENDS 3-14
   .EOM 3-14
   .FFT 11-41 , 28-7
   .FOUR 11-38
   .GLOBAL 3-20
   .GRAPH 8-2 , 8-11 , 8-19
   .IC 10-9 , 10-10
   .INCLUDE 3-29
   initial conditions 10-9
   .LIB 3-32 , 3-33
      call 3-32
      nesting 3-33
   .LOAD 10-11 , 10-13
   .MACRO 3-12
   .MEASURE 8-2 , 8-3 , 8-37 , 9-7 , 9-12
   .MODEL 3-30 , 8-12 , 13-5 , 13-41
   model 14-1
      BJTs 16-4
      junction 15-7
   .NET 12-14
   .NODESET 9-29 , 10-10 , 10-23
   .NOISE 12-11
   .OP 10-6
   .OPTION 9-2 , 10-31
      ACCT 8-16
      ALT999(9) 8-14
      CO 8-14
      INGOLD 8-15
      POST 8-15
   .OPTIONS SEARCH 3-36
   .PARAM 3-37 , 13-39
   .PLOT 8-2 , 8-8 , 8-19
   .PRINT 8-2 , 8-5 , 8-19
   .PROBE 8-2 , 8-10 , 8-19
   .PROTECT 3-40
   .PZ 10-21 , 27-3
   .SAMPLE 12-13
   .SAVE 10-11 , 10-12
   .SENS 10-19
   SHAPE 18-38
   source 3-10
   .SUBCKT 3-12 , 8-38 , 26-65
   .TEMP 3-20 , 13-5 , 13-6
   .TF 10-20
   .TITLE 3-9
   .TRAN 11-4 , 13-5 , 13-39
   .UNPROTECT 3-40
   .WIDTH 8-14
statistical analysis 13-8 - 13-34
statistics
   calculations 13-3
   listing 8-16
   report 9-5
Statz model 17-2 , 17-3 , 17-22
   capacitance equations 17-28
STC-ITT model 20-5
stimulus input files 26-4
STOP .FFT parameter 28-7
strip, defining 18-40
stripline transmission line C-21
structure simulation 1-7
subcircuits
   adder 31-3
   BJTs 16-55
   call statement 3-14
   calling 3-14
   calling tree 3-18
   changing in .ALTER blocks 3-41
   creating reusable circuits 3-47
   element names 3-14
   generator 26-5
   global versus local nodes 3-20
   hierarchical parameters 3-48
   library structure 3-52
   model names 3-14
   multiply parameter 3-15
   multiplying 3-48
   names 3-13
   node names 3-14 , 3-17
      abbreviated 3-18
   node numbers 3-13
   output printing 8-19
   parameter 3-13
      example 24-11
      passing 3-14 , 3-15
   path names 3-18
   power dissipation computation 8-25
   .PRINT and .PLOT statements 3-49
   printing path numbers 9-9
   search order 3-49
   test example 3-13
   zero prefix 3-19
.SUBCKT statement 3-12 , 8-38
   search order 26-65
SUBS model parameter 16-2
substrate
   capacitance equations 16-39
   current equations 16-31
   diodes 16-19
subthreshold current equations, MOSFETs
   LEVEL 13 21-115
   LEVEL 2 21-17
   LEVEL 3 21-28
   LEVEL 38 21-175
   LEVEL 5 21-48
   LEVEL 6 21-73
   LEVEL 8 21-99
surface potential equations 20-109
.sw# file 3-55 , 3-56
sweep
   data 3-25
      storing 9-12
   frequency 12-6
   inner 3-25
   outer 3-25
   variables 31-18
SWEEP keyword 10-16 , 11-6 , 12-6
switch example 5-39
switched capacitor 29-48
   filter example 29-50
switch-level MOSFET's example 5-39
Synopsys models, calibrating 24-1
systems, simulating 25-2

T

T Elements C-2
   lossless transmission line model C-88
   multiplier function M C-5
   transient effects modeling C-75
tabular data 5-61 , 5-64
Taguchi analysis 13-2
tan(x) function 7-9
tanh(x) function 7-9
TARG keyword 8-40
target specification 8-40
Taylor-Huang model 20-5
TC1, TC2 element parameters 26-13 , 26-20 , 26-25 , 26-29 , 29-11
TD
   element parameter 26-13 , 26-20 , 26-25 , 26-29
   keyword 8-33 , 8-43
tdelay (digital vector file) 5-73
TDR
   optimization 25-10
      packaging 25-9
      procedure 25-11
   time domain reflectometry 25-9
TEM transmission lines 18-3
TEMP
   keyword 10-16 , 12-6
   model parameter 3-20 , 13-5 , 26-71
   sweep variable 31-18
.TEMP statement 3-20 - 3-21 , 13-5 , 13-6 - 13-7
temper variable 7-11
temperature
   AC sweep 12-4
   BJTs
      beta equations 16-42 - 16-46
      capacitance equations 16-46
      energy gap equations 16-42
      LEVEL 2 equations 16-49
      parameters 16-14
      parasitic resistor equations 16-49
      saturation equations 16-42 - 16-46
   capacitor equations 14-8
   circuit 13-4 , 13-6
      default 13-5
   coefficients 4-2
      demo 31-18
      G and E Elements 29-11
   compensation
      equations 15-28
         MOSFETs LEVEL 47 22-17
      example 21-30
      MOSFETs BSIM LEVEL 13 21-127
   DC sweep 10-14 , 10-17
   derating 3-20 , 3-21 , 13-5 , 13-7
   diodes 15-19
   effect
      BSIM LEVEL 13 21-116
      MOSFETs LEVEL 39 21-196
      parameters
         BJTs 16-14
         junction diodes 15-19
   element 13-5 , 13-6
   equations
      BJTs 16-42
         LEVEL 2 16-49
      breakdown voltage 15-29
      capacitance 15-31
      contact potential 15-30
      energy gap 15-28
      FJET's and MESFETs 17-38
      grading coefficient 15-32
      leakage 15-29
      MOSFETs 20-105
      resistance 15-32
      resistor 14-8
      transit time 15-29
   inductor 14-17
   JFETs
      equations 17-38 , 17-41 - 17-44
      TLEV parameter 17-38
      TLEVC parameter 17-38
   junction diodes 15-19
   MESFETs equations 17-38 , 17-41 - 17-44
   MOSFETs
      channel length modulation 20-111
      diode
         capacitance 20-106
         resistance 20-111
      equations 20-105
      mobility 20-111
      parameters 20-102
      surface potential 20-109
      threshold voltage 20-110
   optimizing coefficients 31-18
   parameters 17-38
      JFETs 17-38
      JFETs and MESFETs 17-39
      MOSFETs 20-102
         LEVEL 13 21-109
         LEVEL 28 21-154
         LEVEL 49 22-49
         LEVEL 55 22-90
         LEVEL 57 22-126
         LEVELs 49 and 53 22-41
   reference 3-20 , 13-5
      model parameters 14-5
   resistor equations 14-8
   sweeping 31-18
   time sweep 11-4
   variable 7-11
Temperature Variation Analysis 13-2
Texas Instruments device models D-16
.TF statement 10-19 , 26-46
tfall (digital vector file) 5-75
TH model parameter C-15 , C-24
TH1 model parameter C-24
THB model parameter C-15 , C-24
THD (total harmonic distortion) 28-1
The 3-40
thermal noise 14-7
THK1 model parameter C-24
THK2 model parameter C-24
three-dimensional function 5-27
threshold
   temperature equations, JFETs and MESFETs 17-44
   voltage
      BSIM LEVEL 13 21-114
      equations, MOSFETs 20-50
         LEVEL 1 21-6
         LEVEL 13 21-114
         LEVEL 2 21-13
         LEVEL 28 21-156
         LEVEL 3 21-25
         LEVEL 38 21-171
         LEVEL 47 22-10
         LEVEL 5 21-45
         LEVEL 6 21-61
         LEVEL 8 21-95
         temperature 20-110
      parameters, MOSFETs 20-50
         LEVEL 1 21-4
         LEVEL 2 21-9 - 21-10
         LEVEL 3 21-21 - 21-22
         LEVEL 38 21-165
         LEVEL 5 21-35
         LEVEL 8 21-91 - 21-92
         LEVELs 6, 7 21-56 - 21-57
TI model 20-6 , D-16
TIC model parameter 8-13
time 10-7
   delay 8-33
   domain
      algorithm 11-30
      reflectometry 25-9
      to frequency domain 29-1
   maximum 29-6
   resolution 29-5
   sweep 11-4
   variable 7-11
   versus impedance 25-9
    See also CPU time
TimeMill models, calibrating 24-1
TIMERES option 9-47 , 11-19
TIMESCALE model parameter 5-55
timestep
   algorithms 9-44 , 11-12 , 11-33
   calculation for DVDT=3 9-44 , 11-21
   changing size 9-40 , 11-18
   control 9-41 , 9-44 , 9-46 , 11-18 , 11-19 , 11-21 , 18-11
      algorithms 11-32 - 11-35
      DELMAX 11-35
      error C-61
      FS 11-35
      FT 11-35
      minimum internal timestep 11-36
      Minimum Timestep Coefficient 11-36
      options 11-26 , 11-35
         CHGTOL 11-34
         IMAX 11-33
         IMIN 11-33
         RELQ 11-34
         TRTOL 11-34
      RMAX 11-35
      RMIN 11-35
      TSTEP 11-36
   control error C-61
   default control algorithm 11-29
   DVDT algorithm 11-34
   internal 9-43 , 11-20
   local truncation error algorithm 11-34
   maximum 9-45 , 9-46 , 9-47 , 11-21 , 11-22 , 11-23
   minimum 9-45 , 9-46 , 9-48 , 11-22 , 11-23
   reversal 11-34
      definition 9-43 , 11-15
   setting initial 9-43 , 11-20
   transient analysis algorithm 9-48 , 11-13
   variation by HSPICE 9-43 , 11-20
TIMESTEP model parameter 5-55
timing
   analysis 30-1
   constraints 30-1
   failures 30-2
   hold time 30-4
   setup time 30-4
   violation analysis 30-2
title for simulation 3-9
.TITLE statement 3-9
tmp directory 1-12
TMPDIR environment variable 1-12
TNOM option 3-20 , 13-5
TO .FFT parameter 28-7
TO keyword 8-46 , 8-52
TOL 12-13
tolerance options 10-22
TOM model 17-45
   LEVEL 3 parameters 17-45
   parameters 17-46
    See also TriQuint model
TOP keyword 10-13
topology
   check, suppressing 9-8
   supported 23-40
TOX model parameter 13-9
TR model parameter 15-35
.tr# file 3-55 , 3-56
.TRAN statement 13-5 , 13-39
transcapacitance 20-59
transconductance
   FREQ function 29-8
   JFETs and MESFETs 17-8
   LAPLACE function 29-6
   MOSFETs 20-22
   POLE function 29-7
transfer function 10-20
   algebraic 26-3
   analysis 26-46
   coefficients 29-30
   filters 29-31
   frequency domain 27-2 , 29-20
   general form 29-20 , 29-29
   inverse Laplace transform 29-33
   poles 27-2
   reduced form 29-30
   roots 27-2
   voltage gain 29-24
   zeros 27-2
transfer sign function 7-10
TRANSFORMER element parameter 26-14
transformer, behavioral 26-57
transforms, Fourier 29-5
transient
   analysis 8-3
      accuracy 9-38
      Fourier analysis 11-38
      initial conditions 10-9 , 11-3
      inverter 2-7
      MOSFETs, equivalent circuit 20-23
      number of iterations 9-46 , 11-23
      RC network 2-5
      sources 5-5
   lateral 16-22
   modeling 29-2
   output variables 8-21
   vertical 16-23
transistors
   BJTs
      AC analysis 16-23 , 16-24
      AC noise analysis 16-24 , 16-25
      transient analysis 16-22 , 16-23
   field effect 20-16
   isoplanar silicon gate 20-17
   lateral 16-23 , 16-24 , 16-28
      geometry 16-28 , 16-51
   process parameters, MOSFETs
      LEVEL 13 21-102 - 21-106
      LEVEL 28 21-147
      LEVEL 49 22-34
   substrate diodes 16-19
      geometry 16-28
   vertical 16-24 , 16-25 , 16-28
      geometry 16-28 , 16-50
      VBIC 16-57
transit time
   BJTs 16-6
   parameters 16-12
transition files 26-4
Transmission line
   S Element 6-8
transmission line
   resistive termination 6-8
transmission lines
   AC resistance C-19
   analysis guidelines C-83
   attenuation C-88
      calculations C-85
      effects C-94
   bandwidth C-79
   branch capacitances C-33 , C-34
   capacitance
      definitions C-32
      matrix C-52
      to ground C-18
   CEXT parameter C-32
   characteristic impedance C-70 , C-73
   Cjk symbol C-32
   clock frequency C-79
   coax
      example C-57
      models C-25
   common ground inductance C-75
   conductance definitions C-32
   conductor
      length C-32
      resistance C-93
      width C-32
   coupled
      lines C-11
      microstrips example C-59
   crosstalk C-75 , C-78
   CX symbol C-32
   CXY symbol C-32
   delay too small warning C-5
   delays C-37
   dielectric loss C-90
   dispersion C-88
   dissipation C-91
      factor C-89
   dual dielectric C-21
   effects