Performing Worst Case Analysis

Worst case analysis often is used for design and analysis of MOS and BJT IC circuits. The worst case is simulated by taking all variables to their 2-sigma or 3-sigma worst case values. Since it is unlikely that several independent variables will attain their worst case values simultaneously, this technique tends to be overly pessimistic, and can lead to over-designing the circuit. However, it is useful as a fast check.

Model Skew Parameters

Avant! has extended the models in Star-Hspice to include physically measurable model parameters. The parameter variations allow the circuit simulator to predict the actual circuit response to the extremes of the manufacturing process. The physically measurable model parameters are called "skew" parameters because they are skewed from a statistical mean to obtain the predicted performance variations.

Examples of skew parameters are the difference between the drawn and physical dimension of metal, polysilicon, or active layers of an integrated circuit.

Generally, skew parameters are chosen independent of each other, so that combinations of skew parameters can be used to represent worst cases. Typical skew parameters for CMOS technology include:

• XL - polysilicon CD (critical dimension of poly layer representing the difference between drawn and actual size)
• XWn, XWp - active CD (critical dimension of active layer representing the difference between drawn and actual size)
• TOX - gate oxide thickness
• RSHn, RSHp - active layer resistivity
• DELVTOn, DELVTOp- threshold voltage variation

These parameters are allowed in any level MOS model in Star-Hspice. The DELVTO parameter simply shifts the threshold value. It is added to VTO for the Level 3 model and is added to or subtracted from VFB0 for the BSIM model. Sigma Deviations shows whether deviations are added to or subtracted from the average.

Skew parameters are chosen based on the available historical data collected either during fabrication or electrical test. For example, the poly CD skew parameter XL is collected during fabrication. This parameter is usually the most important skew parameter for a MOS process. Historical records produce data as shown in Historical Records for Skew Parameters in a MOS Process.

Figure 13-3: Historical Records for Skew Parameters in a MOS Process

Using Skew Parameters in Star-Hspice

The following example shows how to create a worst case corners library file for a CMOS process model. The physically measured parameter variations must be chosen so that their proper minimum and maximum values are consistent with measured current (IDS) variations. For example, a 3-sigma variation in IDS can be generated from a 2-sigma variation in the physically measured parameters.

Figure 13-4: Worst Case Corners Library File for a CMOS Process Model

The simulator accesses the models and skew through the .LIB library statement and the .INCLUDE include file statement. The library contains parameters that modify .MODEL statements. The following example of .LIB of model skew parameters features both worst case and statistical distribution data. The statistical distribution median value is the default for all non-Monte Carlo analysis.

Example

.LIB TT 

$TYPICAL P-CHANNEL AND N-CHANNEL CMOS LIBRARY DATE:3/4/91

$ PROCESS: 1.0U CMOS, FAB22, STATISTICS COLLECTED 3/90-2/91

$ following distributions are 3 sigma ABSOLUTE GAUSSIAN

.PARAM 

$ polysilicon Critical Dimensions

+ polycd=agauss(0,0.06u,1) xl='polycd-sigma*0.06u' 

$ Active layer Critical Dimensions

+ nactcd=agauss(0,0.3u,1) xwn='nactcd+sigma*0.3u' 

+ pactcd=agauss(0,0.3u,1) xwp='pactcd+sigma*0.3u' 

$ Gate Oxide Critical Dimensions (200 angstrom +/- 10a at 1
$ sigma)

+ toxcd=agauss(200,10,1) tox='toxcd-sigma*10'

$ Threshold voltage variation

+ vtoncd=agauss(0,0.05v,1) delvton='vtoncd-sigma*0.05'

+ vtopcd=agauss(0,0.05v,1) delvtop='vtopcd+sigma*0.05'

.INC `/usr/meta/lib/cmos1_mod.dat'						$ model include file

.ENDL TT

.LIB FF

$HIGH GAIN P-CH AND N-CH CMOS LIBRARY 3SIGMA VALUES

.PARAM TOX=230 XL=-0.18u DELVTON=-.15V DELVTOP= 0.15V

.INC `/usr/meta/lib/cmos1_mod.dat'						$ model include file

.ENDL FF

The model would be contained in the include file /usr/meta/lib/cmos1_mod.dat.

.MODEL NCH NMOS LEVEL=2 XL=XL TOX=TOX DELVTO=DELVTON .....

.MODEL PCH PMOS LEVEL=2 XL=XL TOX=TOX DELVTO=DELVTOP .....

Skew File Interface to Device Models

The skew parameters are model parameters. They are used most often for transistor models, but they also apply to passive components. A typical device model set includes:

• MOSFET models for all device sizes using automatic model selector
• RC wire models for polysilicon, metal1, and metal2 layers (These models include temperature coefficients and fringing capacitance. They apply to drawn dimension)
• Single and distributed diode models for N+,P+, and well (includes temperature, leakage, and capacitance based on drawn dimension)
• BJT models for parasitic bipolar transistors, as well as any special BJTs such as a BiCMOS for ECL BJT process (includes current and capacitance as a function of temperature)
• Metal1 and metal2 transmission line models for long metal lines
• Models must be able to accept elements with sizes based on drawn dimension. A cell might be drawn at 2 µ dimension, shrink to 1 µ, with a physical size of 0.9 µ and an effective electrical size of 0.8 µ. The following dimension levels must be accounted for:

drawn size
shrunken size
physical size
electrical size

Figure 13-5: Device Model from Drawn to Electrical Size